diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-04 21:45:52 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-05 23:38:38 +0200 |
| commit | 3bde3d74c5574d7855d1845130bdd357bd2cb7e4 (patch) | |
| tree | b7f58f0207c6df21c857351673dfd0c1dcaf65af /src/mainboard/google/rambi/acpi/mainboard.asl | |
| parent | 014baea1ceda67aa5df8bb4fbf20782893915f81 (diff) | |
baytrail: interrupt routing support
This provides the initial support for interrupt routing
in bay trail. It includes both acpi changes and board changes
to ensure the interdependencies are met with the current ASL
code. The PIRQ routing is handled by the mainboard exporting
an irqroute.h header that describes the per device and PIRQ
PCI settings.
There are still a lot of ACPI errors in the kernel with this
change, though.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted rambi into kernel.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
Reviewed-on: https://chromium-review.googlesource.com/175700
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4940
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/rambi/acpi/mainboard.asl')
| -rw-r--r-- | src/mainboard/google/rambi/acpi/mainboard.asl | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 3e0eb339ee..948d7dfe87 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Google Inc. + * Copyright (C) 2012 Google Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,10 +19,20 @@ * MA 02110-1301 USA */ -Device (PWRB) +Scope (\_SB) { - Name(_HID, EisaId("PNP0C0C")) + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } - // Wake from deep sleep via GPIO27 - Name(_PRW, Package(){27, 4}) + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } } |