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authorDivya Chellap <divya.chellappa@intel.com>2017-12-19 20:16:50 +0530
committerMartin Roth <martinroth@google.com>2017-12-22 16:43:17 +0000
commite7fb7ce06577d88a193c8553b2d94c12eb256c58 (patch)
treee14ad6b678a80c6112dfc0f67e84ba9c1094e8ca /src/mainboard/google/rambi/Makefile.inc
parent361d197d7789f1a974eff05c7a6d7debc0929646 (diff)
soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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