diff options
| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2019-11-01 12:16:03 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-02 12:58:28 +0000 |
| commit | c0b9c8cbc014662dccdab98841a47dca2570dc0d (patch) | |
| tree | 1954c7468d1ccd39d8330c1a632a7eba6ea7827b /src/mainboard/google/poppy | |
| parent | ecfb4b81aeb91b94a20b57d7229e1a9da9d4722f (diff) | |
mb/google/poppy: Rework OV5670 power on sequence
In particular:
- Enable regulators *after* configuring the voltage
- Allow 1 ms for the voltages to settle
- Enable clock after powering on regulators
- Remove extra delays between enabling things. The sensor requires 8192
clock cycles after the reset is lifted before I²C access, so 1 ms is
enough.
- Make the delay after lifting xshutdown 10 ms. This guarantees that
streaming will only start once the sensor has had enough time to settle
after lifting the reset.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/poppy')
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 12c3c22e1b..355b25528e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -526,30 +526,39 @@ Scope (\_SB.PCI0.I2C2) daisy chain */ DOVD(1) - VAX2 = 1 /* Enable VAUX2 */ - if (LNotEqual (AX2V, 52)) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 } - Sleep(1) + VAX2 = 1 /* Enable VAUX2 */ - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE1 = 1 + \_SB.PCI0.I2C2.PMIC.CGP4(1) + + /* + * Wait for DOVDD and AVDD + * to settle. + */ + Sleep(1) - VAX1 = 1 /* Enable VAUX1 */ if (LNotEqual (AX1V, 19)) { /* Set VAUX1 as 1.2132V */ AX1V = 19 } - Sleep(3) + VAX1 = 1 /* Enable VAUX1 */ - \_SB.PCI0.I2C2.PMIC.CGP4(1) - Sleep(3) + /* Wait for VDD to settle. */ + Sleep(1) + + \_SB.PCI0.I2C2.PMIC.CLKE() + CLE1 = 1 \_SB.PCI0.I2C2.PMIC.CGP5(1) - Sleep(3) + /* + * Ensure 10 ms between + * power-up and streamon. + */ + Sleep(10) STA = 1 } } |