diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-10 01:24:11 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:13:23 +0000 |
| commit | 97c5464443306f26b61cec3a0f50108a5c06b7ef (patch) | |
| tree | f085457907ad200a0d9d9be8a07c937e755fae91 /src/mainboard/google/poppy | |
| parent | 19c2ce7639d55908d210782ae5a0315396cc7eaf (diff) | |
skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy')
10 files changed, 42 insertions, 18 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index b7ab523877..ce943c486c 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -70,9 +70,11 @@ chip soc/intel/skylake register "PmTimerDisabled" = "1" register "speed_shift_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "15" - register "psys_pmax" = "45" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 7974a289d3..ea7ee8fdc4 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/power_limit.h> #define PL2_AML 18 #define PL2_KBL 15 @@ -25,8 +26,10 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { + struct soc_power_limits_config *soc_conf; config_t *cfg = config_of_soc(); + soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - cfg->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 77725349e7..0f3cc0443f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -267,9 +267,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index e4d148c3e2..4fa41c55ca 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -288,7 +288,9 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tcc_offset" = "3" # TCC of 97C - register "psys_pmax" = "101" + register "power_limits_config" = "{ + .psys_pmax = 101, + }" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 648e0d0647..8d5d0c482b 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -10,6 +10,7 @@ #include <drivers/intel/gma/opregion.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/mp_init.h> +#include <intelblocks/power_limit.h> #include <smbios.h> #include <soc/ramstage.h> #include <string.h> @@ -279,8 +280,11 @@ void variant_devtree_update(void) break; } + struct soc_power_limits_config *soc_conf; + soc_conf = &cfg->power_limits_config; + /* Update PL2 based on SKU. */ - cfg->tdp_pl2_override = get_pl2(pl2_id); + soc_conf->tdp_pl2_override = get_pl2(pl2_id); /* Overwrite settings for different projects based on OEM ID*/ oem_index = find_sku_mapping(read_oem_id()); diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index c3404bf4f8..c55562d0ec 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -288,9 +288,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 96fcc39e65..8819350dce 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -66,9 +66,11 @@ chip soc/intel/skylake # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "18" - register "psys_pmax" = "45" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 18, + .psys_pmax = 45, + }" register "tcc_offset" = "10" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 8d72144f9b..1482b3458f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/power_limit.h> /* PL2 limit in watts for AML and KBL */ #define PL2_AML 18 @@ -26,8 +27,10 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { + struct soc_power_limits_config *soc_conf; config_t *cfg = config_of_soc(); + soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - cfg->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 65578708ad..de7023dacb 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -246,9 +246,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 18W for AML-Y - register "tdp_pl2_override" = "18" + register "power_limits_config" = "{ + .tdp_pl2_override = 18, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 146d8d2c19..8c22adea2f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -268,9 +268,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration |