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authorFelix Singer <felixsinger@posteo.net>2024-06-23 00:25:18 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-26 11:43:56 +0000
commit6c83a71b0a803c922b02b613e927d4c49b944c32 (patch)
tree176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/google/poppy
parentc7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff)
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/google/poppy')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb20
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb28
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb32
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb30
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb22
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb25
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb28
7 files changed, 104 insertions, 81 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 181c77b999..8b821f6ecf 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -140,15 +140,6 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
- # USB 2.0
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
- register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
-
- # USB 3.0
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -231,6 +222,17 @@ chip soc/intel/skylake
device ref imgu on end
device ref ish off end
device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_LONG(OC0), // Type-C Port 1
+ [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
+ [4] = USB2_PORT_LONG(OC1), // Type-C Port 2
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
+ [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
+ }"
+
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 0317139b7c..8fbed5a853 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -130,17 +130,6 @@ chip soc/intel/skylake
# RP 1 uses CLK SRC 1
register "PcieRpClkSrcNumber[0]" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -251,7 +240,22 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_LONG(OC0), // Type-C Port 1
+ [1] = USB2_PORT_MID(OC_SKIP), // Type-A Port
+ [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
+ [4] = USB2_PORT_LONG(OC1), // Type-C Port 2
+ [6] = USB2_PORT_MID(OC_SKIP), // Type-A Port
+ [8] = USB2_PORT_MID(OC_SKIP), // Type-A Port
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
+ [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-A Port
+ }"
+ end
device ref south_xdci on end
device ref thermal on end
device ref cio on end
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 2bb5e112c8..c851c37432 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -167,19 +167,6 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0
- register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1
- register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader
-
# Touchscreen
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
@@ -276,7 +263,24 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu off end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_LONG(OC0), // Type-C Port 0
+ [1] = USB2_PORT_LONG(OC1), // Type-C Port 1
+ [2] = USB2_PORT_MID(OC2), // Type-A Port
+ [3] = USB2_PORT_MID(OC_SKIP), // Card reader
+ [4] = USB2_PORT_MID(OC_SKIP), // WiFi
+ [5] = USB2_PORT_MID(OC_SKIP), // Rear camera
+ [6] = USB2_PORT_MID(OC_SKIP), // Front camera
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 0
+ [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 1
+ [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // Card reader
+ }"
+ end
device ref south_xdci on end
device ref thermal on end
device ref cio off end
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 29233c9d2a..122fb153c3 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -148,18 +148,6 @@ chip soc/intel/skylake
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)" # Type-A Port
- register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)" # Type-C Port 2
- register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1
- register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LTE module
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -282,7 +270,23 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_LONG(OC1), // Type-C Port 1
+ [1] = USB2_PORT_SHORT(OC2), // Type-A Port
+ [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
+ [4] = USB2_PORT_LONG(OC0), // Type-C Port 2
+ [6] = USB2_PORT_SHORT(OC_SKIP), // H1
+ [8] = USB2_PORT_SHORT(OC_SKIP), // Camera
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC1), // Type-C Port 1
+ [1] = USB3_PORT_DEFAULT(OC0), // Type-C Port 2
+ [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // LTE module
+ }"
+ end
device ref south_xdci on end
device ref thermal on end
device ref cio on end
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 1ef0b454ab..140f5f864b 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -147,16 +147,6 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
- # USB 2.0
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
- register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
- register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # pogo port
-
- # USB 3.0
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -247,6 +237,18 @@ chip soc/intel/skylake
device ref sa_thermal on end
device ref imgu on end
device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_LONG(OC0), // Type-C Port 1
+ [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
+ [4] = USB2_PORT_LONG(OC1), // Type-C Port 2
+ [6] = USB2_PORT_LONG(OC_SKIP), // pogo port
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
+ [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
+ }"
+
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 42528cfe0e..823df7cdd0 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -137,17 +137,6 @@ chip soc/intel/skylake
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
- register "usb2_ports[0]" = "USB2_PORT_SHORT(OC0)" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-A Port
- register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
- register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1
- register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -233,6 +222,20 @@ chip soc/intel/skylake
device ref sa_thermal on end
device ref imgu off end
device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_SHORT(OC0), // Type-C Port 1
+ [1] = USB2_PORT_LONG(OC3), // Type-A Port
+ [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth
+ [4] = USB2_PORT_LONG(OC1), // Type-C Port 2
+ [6] = USB2_PORT_SHORT(OC_SKIP), // H1
+ [8] = USB2_PORT_SHORT(OC_SKIP), // Camera
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
+ [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
+ [2] = USB3_PORT_DEFAULT(OC3), // Type-A Port
+ }"
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index fb8aad2236..e877260887 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -139,17 +139,6 @@ chip soc/intel/skylake
# RP 1 uses CLK SRC 1
register "PcieRpClkSrcNumber[0]" = "1"
- register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-C Port 2
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -261,7 +250,22 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref imgu on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_LONG(OC0), // Type-C Port 1
+ [1] = USB2_PORT_MID(OC_SKIP), // Type-A Port
+ [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
+ [4] = USB2_PORT_MAX(OC1), // Type-C Port 2
+ [6] = USB2_PORT_MID(OC_SKIP), // Type-A Port
+ [8] = USB2_PORT_MID(OC_SKIP), // Type-A Port
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1
+ [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-A Port
+ }"
+ end
device ref south_xdci on end
device ref thermal on end
device ref cio on end
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 08:06:13 +0000