mb/google/poppy/variants/nocturne: configure the FPMCU interface

The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.

We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.

BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.

Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 25 insertions, 9 deletions

diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 621bbe495d..91e8b46cf1 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -11,7 +11,7 @@ chip soc/intel/skylake
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
+	register "gpe0_dw0" = "GPP_C"
 	register "gpe0_dw1" = "GPP_D"
 	register "gpe0_dw2" = "GPP_E"
 
@@ -326,7 +326,23 @@ chip soc/intel/skylake
 				device spi 0 on end
 			end
 		end # GSPI #0
-		device pci 1e.3 on  end # GSPI #1
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)"
+				register "wake" = "GPE0_DW0_09" # GPP_C9
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+				register "reset_delay_ms" = "0"
+				register "reset_off_delay_ms" = "0"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
+				register "enable_delay_ms" = "0"
+				register "enable_off_delay_ms" = "0"
+				register "has_power_resource" = "1"
+				device spi 0 on end
+			end
+		end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 off end # SDCard
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index bd38a20fdd..be76b64267 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -39,8 +39,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NC(GPP_A10),
 	/* A11 : PCH_FP_PWR_EN */
 	PAD_CFG_GPO(GPP_A11, 0, DEEP),
-	/* A12 : FPMCU_INT */
-	PAD_CFG_GPI_APIC(GPP_A12, NONE, DEEP),
+	/* A12 : ISH_GP6 */
+	PAD_CFG_NC(GPP_A12),
 	/* A13 : SUSWARN# ==> SUSWARN_L */
 	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
 	/* A14 : ESPI_RESET# */
@@ -108,7 +108,7 @@ static const struct pad_config gpio_table[] = {
 	/* B21 : GSPI1_MISO ==> PCH_FPMCU_SPI_MISO_R */
 	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
 	/* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */
-	PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
+	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
 	/* B23 : SM1ALERT# ==> PCHHOT# */
 	PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2),
 
@@ -129,13 +129,13 @@ static const struct pad_config gpio_table[] = {
 	/* C7  : SM1DATA ==> NC */
 	PAD_CFG_NC(GPP_C7),
 	/* C8  : UART0_RXD ==> PCH_FPMCU_BOOT0 */
-	PAD_CFG_NC(GPP_C8),
+	PAD_CFG_GPO(GPP_C8, 0, DEEP),
 	/* C9  : UART0_TXD ==> FPMCU_INT */
-	PAD_CFG_NC(GPP_C9),
+	PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT),
 	/* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */
-	PAD_CFG_NC(GPP_C10),
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
 	/* C11 : UART0_CTS# ==> FPMCU_INT */
-	PAD_CFG_NC(GPP_C11),
+	PAD_CFG_GPI_APIC_INVERT(GPP_C11, NONE, DEEP),
 	/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
 	/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */