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authorFurquan Shaikh <furquan@chromium.org>2017-12-04 17:41:44 -0800
committerFurquan Shaikh <furquan@google.com>2017-12-07 07:53:37 +0000
commit903472c3c8ba80495b108ed507142b8e879b7b1a (patch)
tree8588826a1b67044ce55da36122815b9d33bf1e39 /src/mainboard/google/poppy/variants
parent48be29e3920aef1254eca97298c4155864e72fc8 (diff)
mb/google/poppy/variants/nami: Add support for nami board
This change adds variant nami derived from baseboard poppy. BUG=b:70160119 Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants')
-rw-r--r--src/mainboard/google/poppy/variants/nami/Makefile.inc7
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb302
-rw-r--r--src/mainboard/google/poppy/variants/nami/gpio.c388
-rw-r--r--src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl16
-rw-r--r--src/mainboard/google/poppy/variants/nami/include/variant/ec.h85
-rw-r--r--src/mainboard/google/poppy/variants/nami/include/variant/gpio.h40
-rw-r--r--src/mainboard/google/poppy/variants/nami/pl2.c48
7 files changed, 886 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc
new file mode 100644
index 0000000000..0050a3b3bd
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc
@@ -0,0 +1,7 @@
+
+SPD_SOURCES = empty # 0b0000
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += pl2.c
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
new file mode 100644
index 0000000000..401e1372ef
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -0,0 +1,302 @@
+chip soc/intel/skylake
+
+ # Deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "1"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataMode" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "EnableTraceHub" = "0"
+ register "XdciEnable" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "SaImguEnable" = "0"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "0"
+ register "IshEnable" = "0"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "FspSkipMpInit" = "1"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 2A | 2A | 2A | 2A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 5A | 24A | 24A | 24A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 |
+ #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 |
+ #+----------------+-------+-------+-------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(5),
+ .voltage_limit = 1520,
+ .ac_loadline = 1500,
+ .dc_loadline = 1430,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ .ac_loadline = 570,
+ .dc_loadline = 483,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ .ac_loadline = 550,
+ .dc_loadline = 420,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(2),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(24),
+ .voltage_limit = 1520,
+ .ac_loadline = 550,
+ .dc_loadline = 420,
+ }"
+
+ # Root port 4 (x1)
+ # PcieRpEnable: Enable root port
+ # PcieRpClkReqSupport: Enable CLKREQ#
+ # PcieRpClkReqNumber: Uses SRCCLKREQ1#
+ # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+ # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpClkReqSupport[3]" = "1"
+ register "PcieRpClkReqNumber[3]" = "1"
+ register "PcieRpAdvancedErrorReporting[3]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+
+ # Root port 5 (x4)
+ # PcieRpEnable: Enable root port
+ # PcieRpClkReqSupport: Enable CLKREQ#
+ # PcieRpClkReqNumber: Uses SRCCLKREQ3#
+ # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+ # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "3"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+
+ # Root port 9 (x2)
+ # PcieRpEnable: Enable root port
+ # PcieRpClkReqSupport: Enable CLKREQ#
+ # PcieRpClkReqNumber: Uses SRCCLKREQ2#
+ # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+ # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "2"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0
+ register "usb2_ports[1]" = "USB2_PORT_LONG(OC1)" # Type-C Port 1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Card reader
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WiFi
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Rear camera
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Front camera
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader
+
+ # Touchscreen
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
+
+ # Trackpad
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"
+
+ # Pen
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
+
+ # Audio
+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
+
+ # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
+ # communication before memory is up.
+ register "gspi[0]" = "{
+ .speed_mhz = 1,
+ .early_init = 1,
+ }"
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexSpi0] = PchSerialIoPci,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+ }"
+
+ register "speed_shift_enable" = "1"
+
+ register "tcc_offset" = "10" # TCC of 90C
+
+ # Lock Down
+ register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_PCI_EXP"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
new file mode 100644
index 0000000000..81fb12949c
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -0,0 +1,388 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+ /* A0 : RCIN# ==> NC(TP22) */
+ PAD_CFG_NC(GPP_A0),
+ /* A1 : ESPI_IO0 */
+ /* A2 : ESPI_IO1 */
+ /* A3 : ESPI_IO2 */
+ /* A4 : ESPI_IO3 */
+ /* A5 : ESPI_CS# */
+ /* A6 : SERIRQ ==> NC(TP24) */
+ PAD_CFG_NC(GPP_A6),
+ /* A7 : PIRQA# ==> NC(TP15) */
+ PAD_CFG_NC(GPP_A7),
+ /* A8 : CLKRUN# ==> NC(TP23) */
+ PAD_CFG_NC(GPP_A8),
+ /* A9 : ESPI_CLK */
+ /* A10 : CLKOUT_LPC1 ==> NC */
+ PAD_CFG_NC(GPP_A10),
+ /* A11 : PME# ==> NC(TP46) */
+ PAD_CFG_NC(GPP_A11),
+ /* A12 : BM_BUSY# ==> NC */
+ PAD_CFG_NC(GPP_A12),
+ /* A13 : SUSWARN# ==> SUSWARN#_R */
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+ /* A14 : ESPI_RESET# */
+ /* A15 : SUSACK# ==> SUSACK# */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* A16 : SD_1P8_SEL ==> NC */
+ PAD_CFG_NC(GPP_A16),
+ /* A17 : SD_PWR_EN# ==> NC */
+ PAD_CFG_NC(GPP_A17),
+ /* A18 : ISH_GP0 ==> NC */
+ PAD_CFG_NC(GPP_A18),
+ /* A19 : ISH_GP1 ==> NC */
+ PAD_CFG_NC(GPP_A19),
+ /* A20 : ISH_GP2 ==> NC */
+ PAD_CFG_NC(GPP_A20),
+ /* A21 : ISH_GP3 ==> NC */
+ PAD_CFG_NC(GPP_A21),
+ /* A22 : ISH_GP4 ==> PCH_SPK_EN */
+ PAD_CFG_GPO(GPP_A22, 1, DEEP),
+ /* A23 : ISH_GP5 ==> NC */
+ PAD_CFG_NC(GPP_A23),
+
+ /* B0 : CORE_VID0 ==> NC(T3) */
+ PAD_CFG_NC(GPP_B0),
+ /* B1 : CORE_VID1 ==> NC(T4) */
+ PAD_CFG_NC(GPP_B1),
+ /* B2 : VRALERT# ==> NC */
+ PAD_CFG_NC(GPP_B2),
+ /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */
+ PAD_CFG_GPO(GPP_B3, 0, DEEP),
+ /* B4 : CPU_GP3 ==> NC */
+ PAD_CFG_NC(GPP_B4),
+ /* B5 : SRCCLKREQ0# ==> NC */
+ PAD_CFG_NC(GPP_B5),
+ /* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* B7 : SRCCLKREQ2# ==> CLKREQ_PCIE#2 */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ /* B8 : SRCCLKREQ3# ==> CLKREQ_PCIE#3 */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+ /* B9 : SRCCLKREQ4# ==> WLAN_PE_RST_AP */
+ PAD_CFG_GPO(GPP_B9, 0, RSMRST),
+ /* B10 : SRCCLKREQ5# ==> NC */
+ PAD_CFG_NC(GPP_B10),
+ /* B11 : EXT_PWR_GATE# ==> NC */
+ PAD_CFG_NC(GPP_B11),
+ /* B12 : SLP_S0# ==> PM_SLP_R_S0# */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* B13 : PLTRST# ==> PLT_RST#_PCH */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* B14 : SPKR ==> NC */
+ PAD_CFG_NC(GPP_B14),
+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* B19 : GSPI1_CS# ==> NC(TP26) */
+ PAD_CFG_NC(GPP_B19),
+ /* B20 : GSPI1_CLK ==> NC(TP27) */
+ PAD_CFG_NC(GPP_B20),
+ /* B21 : GSPI1_MISO ==> NC(TP28) */
+ PAD_CFG_NC(GPP_B21),
+ /* B22 : GSPI1_MOSI ==> NC(TP30) */
+ PAD_CFG_NC(GPP_B22),
+ /* B23 : SM1ALERT# ==> NC */
+ PAD_CFG_NC(GPP_B23),
+
+ /* C0 : SMBCLK ==> NC */
+ PAD_CFG_NC(GPP_C0),
+ /* C1 : SMBDATA ==> NC */
+ PAD_CFG_NC(GPP_C1),
+ /* C2 : SMBALERT# ==> NC(TP917) */
+ PAD_CFG_NC(GPP_C2),
+ /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */
+ PAD_CFG_GPO(GPP_C3, 0, DEEP),
+ /* C4 : SML0DATA ==> NC */
+ PAD_CFG_NC(GPP_C4),
+ /* C5 : SML0ALERT# ==> NC */
+ PAD_CFG_NC(GPP_C5),
+ /* C6 : SM1CLK ==> EC_IN_RW_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
+ /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */
+ PAD_CFG_GPO(GPP_C7, 1, DEEP),
+ /* C8 : UART0_RXD ==> NC(TP31) */
+ PAD_CFG_NC(GPP_C8),
+ /* C9 : UART0_TXD ==> NC(TP32) */
+ PAD_CFG_NC(GPP_C9),
+ /* C10 : UART0_RTS# ==> EN_PP3300_DX_CAM1 */
+ PAD_CFG_GPO(GPP_C10, 1, DEEP),
+ /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM2 */
+ PAD_CFG_GPO(GPP_C11, 1, DEEP),
+ /* C12 : UART1_RXD ==> PCH_MEM_CONFIG0 */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
+ /* C13 : UART1_TXD ==> PCH_MEM_CONFIG1 */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
+ /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG2 */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
+ /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG3 */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
+ /* C16 : I2C0_SDA ==> I2C_0_SDA */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* C17 : I2C0_SCL ==> I2C_0_SCL */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* C18 : I2C1_SDA ==> I2C_1_SDA */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* C19 : I2C1_SCL ==> I2C_1_SCL */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_C22, 0, DEEP),
+ /* C23 : UART2_CTS# ==> PCH_WP */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+
+ /* D0 : SPI1_CS# ==> NC */
+ PAD_CFG_NC(GPP_D0),
+ /* D1 : SPI1_CLK ==> PEN_IRQ# */
+ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),
+ /* D2 : SPI1_MISO ==> PEN_PDCT# */
+ PAD_CFG_GPI_APIC(GPP_D2, NONE, PLTRST),
+ /* D3 : SPI1_MOSI ==> PEN_RST# */
+ PAD_CFG_GPO(GPP_D3, 0, DEEP),
+ /* D4 : FASHTRIG ==> NC */
+ PAD_CFG_NC(GPP_D4),
+ /* D5 : ISH_I2C0_SDA ==> NC */
+ PAD_CFG_NC(GPP_D5),
+ /* D6 : ISH_I2C0_SCL ==> NC */
+ PAD_CFG_NC(GPP_D6),
+ /* D7 : ISH_I2C1_SDA ==> NC */
+ PAD_CFG_NC(GPP_D7),
+ /* D8 : ISH_I2C1_SCL ==> NC */
+ PAD_CFG_NC(GPP_D8),
+ /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),
+ /* D10 : ISH_SPI_CLK ==> NC(TP29) */
+ PAD_CFG_NC(GPP_D10),
+ /* D11 : ISH_SPI_MISO ==> NC */
+ PAD_CFG_NC(GPP_D11),
+ /* D12 : ISH_SPI_MOSI ==> NC */
+ PAD_CFG_NC(GPP_D12),
+ /* D13 : ISH_UART0_RXD ==> NC */
+ PAD_CFG_NC(GPP_D13),
+ /* D14 : ISH_UART0_TXD ==> NC */
+ PAD_CFG_NC(GPP_D14),
+ /* D15 : ISH_UART0_RTS# ==> NC */
+ PAD_CFG_NC(GPP_D15),
+ /* D16 : ISH_UART0_CTS# ==> NC */
+ PAD_CFG_NC(GPP_D16),
+ /* D17 : DMIC_CLK1 ==> SOC_DMIC_CLK1 */
+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+ /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1 */
+ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0 */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0 */
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+ /* D21 : SPI1_IO2 ==> NC */
+ PAD_CFG_NC(GPP_D21),
+ /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
+ PAD_CFG_GPO(GPP_D22, 1, DEEP),
+ /* D23 : I2S_MCLK ==> NC */
+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+
+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+ /* E1 : SATAXPCIE1 ==> SATA_GP1 */
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+ /* E2 : SATAXPCIE2 ==> NC(TP916) */
+ PAD_CFG_NC(GPP_E2),
+ /* E3 : CPU_GP0 ==> TRACKPAD_INT# */
+ PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST),
+ /* E4 : SATA_DEVSLP0 ==> DEVSLP0 */
+ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+ /* E5 : SATA_DEVSLP1 ==> NC(TP914) */
+ PAD_CFG_NC(GPP_E5),
+ /* E6 : SATA_DEVSLP2 ==> NC(TP915) */
+ PAD_CFG_NC(GPP_E6),
+ /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */
+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
+ /* E8 : SATALED# ==> NC */
+ PAD_CFG_NC(GPP_E8),
+ /* E9 : USB2_OCO# ==> USB_C0_OC# */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ /* E10 : USB2_OC1# ==> USB_C1_OC# */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+ /* E11 : USB2_OC2# ==> USB_A0_OC# */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+ /* E12 : USB2_OC3# ==> NC */
+ PAD_CFG_NC(GPP_E12),
+ /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */
+ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
+ /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
+ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
+ /* E15 : DDPD_HPD2 ==> NC */
+ PAD_CFG_NC(GPP_E15),
+ /* E16 : DDPE_HPD3 ==> NC(TP17) */
+ PAD_CFG_NC(GPP_E16),
+ /* E17 : EDP_HPD ==> EDP_HPD */
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+ /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+ /* E19 : DDPB_CTRLDATA ==> SOC_DP1_CTRL_DATA */
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+ /* E20 : DDPC_CTRLCLK ==> SOC_DP2_CTRL_CLK */
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+ /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+ /* E22 : DDPD_CTRLCLK ==> NC */
+ PAD_CFG_NC(GPP_E22),
+ /* E23 : DDPD_CTRLDATA ==> NC */
+ PAD_CFG_NC(GPP_E23),
+
+ /* The next 4 pads are for bit banging the amplifiers, default to I2S */
+ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+ /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+ /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+ /* F3 : I2S2_RXD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
+ /* F4 : I2C2_SDA ==> I2C_2_SDA */
+ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
+ /* F5 : I2C2_SCL ==> I2C_2_SCL */
+ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
+ /* F6 : I2C3_SDA ==> I2C_3_SDA */
+ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
+ /* F7 : I2C3_SCL ==> I2C_3_SCL */
+ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
+ /* F8 : I2C4_SDA ==> NC */
+ PAD_CFG_NC(GPP_F8),
+ /* F9 : I2C4_SCL ==> NC */
+ PAD_CFG_NC(GPP_F9),
+ /* F10 : I2C5_SDA ==> NC */
+ PAD_CFG_NC(GPP_F10),
+ /* F11 : I2C5_SCL ==> NC */
+ PAD_CFG_NC(GPP_F11),
+ /* F12 : EMMC_CMD ==> EMMC_CMD */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+ /* F13 : EMMC_DATA0 ==> EMMC_DATA0 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+ /* F14 : EMMC_DATA1 ==> EMMC_DATA1 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+ /* F15 : EMMC_DATA2 ==> EMMC_DATA2 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+ /* F16 : EMMC_DATA3 ==> EMMC_DATA3 */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+ /* F17 : EMMC_DATA4 ==> EMMC_DATA4 */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+ /* F18 : EMMC_DATA5 ==> EMMC_DATA5 */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+ /* F19 : EMMC_DATA6 ==> EMMC_DATA6 */
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ /* F20 : EMMC_DATA7 ==> EMMC_DATA7 */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ /* F21 : EMMC_RCLK ==> EMMC_RCLK */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ /* F22 : EMMC_CLK ==> EMMC_CLK */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* F23 : RSVD ==> NC */
+ PAD_CFG_NC(GPP_F23),
+
+ /* G0 : SD_CMD ==> NC */
+ PAD_CFG_NC(GPP_G0),
+ /* G1 : SD_DATA0 ==> NC */
+ PAD_CFG_NC(GPP_G1),
+ /* G2 : SD_DATA1 ==> NC */
+ PAD_CFG_NC(GPP_G2),
+ /* G3 : SD_DATA2 ==> NC */
+ PAD_CFG_NC(GPP_G3),
+ /* G4 : SD_DATA3 ==> NC */
+ PAD_CFG_NC(GPP_G4),
+ /* G5 : SD_CD# ==> NC */
+ PAD_CFG_NC(GPP_G5),
+ /* G6 : SD_CLK ==> NC */
+ PAD_CFG_NC(GPP_G6),
+ /* G7 : SD_WP ==> NC */
+ PAD_CFG_NC(GPP_G7),
+
+ /* GPD0: BATLOW# ==> PCH_BATLOW# */
+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+ /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */
+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R# */
+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+ /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_R_BTN# */
+ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+ /* GPD4: SLP_S3# ==> SLP_S3# */
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+ /* GPD5: SLP_S4# ==> SLP_S4# */
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+ /* GPD6: SLP_A# ==> NC(TP44) */
+ PAD_CFG_NC(GPD6),
+ /* GPD7: RSVD ==> NC */
+ PAD_CFG_NC(GPD7),
+ /* GPD8: SUSCLK ==> PCH_SUSCLK */
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+ /* GPD9: SLP_WLAN# ==> NC(TP41) */
+ PAD_CFG_NC(GPD9),
+ /* GPD10: SLP_S5# ==> NC(TP38) */
+ PAD_CFG_NC(GPD10),
+ /* GPD11: LANPHYC ==> NC */
+ PAD_CFG_NC(GPD11),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+
+ /* Ensure UART pins are in native mode for H1. */
+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+
+ /* C23 : UART2_CTS# ==> PCH_WP */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+
+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..216b76f157
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Dummy file until DPTF support is added. */
diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/ec.h b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h
new file mode 100644
index 0000000000..c22f289df9
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/ec.h
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#include <variant/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TABLET_EVENT
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
new file mode 100644
index 0000000000..3dfe92f814
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_C6
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C13
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_C15
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/poppy/variants/nami/pl2.c b/src/mainboard/google/poppy/variants/nami/pl2.c
new file mode 100644
index 0000000000..6744f2c407
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nami/pl2.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <chip.h>
+#include <device/device.h>
+#include <intelblocks/mp_init.h>
+
+#define PL2_I7_SKU 44
+#define PL2_DEFAULT 29
+
+static uint32_t nami_get_pl2(void)
+{
+ struct cpuid_result cpuidr;
+
+ cpuidr = cpuid(1);
+ if (cpuidr.eax == CPUID_KABYLAKE_Y0)
+ return PL2_I7_SKU;
+
+ return PL2_DEFAULT;
+}
+
+static void nami_enable(device_t dev)
+{
+ struct device *root = SA_DEV_ROOT;
+ config_t *conf = root->chip_info;
+
+ if (!conf)
+ return;
+
+ conf->tdp_pl2_override = nami_get_pl2();
+}
+
+struct chip_operations nami_ops = {
+ .enable_dev = nami_enable,
+};