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authorDivya Chellap <divya.chellappa@intel.com>2017-12-19 20:16:50 +0530
committerMartin Roth <martinroth@google.com>2017-12-22 16:43:17 +0000
commite7fb7ce06577d88a193c8553b2d94c12eb256c58 (patch)
treee14ad6b678a80c6112dfc0f67e84ba9c1094e8ca /src/mainboard/google/poppy/variants
parent361d197d7789f1a974eff05c7a6d7debc0929646 (diff)
soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants')
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb2
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb6
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb2
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb2
4 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 2ddf22a948..aaf6ea2b57 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -156,6 +156,8 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
+ # RP 1 uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 4f88f707e1..5e23d45a5f 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -148,11 +148,13 @@ chip soc/intel/skylake
# PcieRpEnable: Enable root port
# PcieRpClkReqSupport: Enable CLKREQ#
# PcieRpClkReqNumber: Uses SRCCLKREQ1#
+ # PcieRpClkSrcNumber: Uses 1
# PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
# PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
register "PcieRpEnable[3]" = "1"
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "1"
+ register "PcieRpClkSrcNumber[3]" = "1"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
@@ -160,11 +162,13 @@ chip soc/intel/skylake
# PcieRpEnable: Enable root port
# PcieRpClkReqSupport: Enable CLKREQ#
# PcieRpClkReqNumber: Uses SRCCLKREQ3#
+ # PcieRpClkSrcNumber: Uses 3
# PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
# PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
+ register "PcieRpClkSrcNumber[4]" = "3"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
@@ -172,11 +176,13 @@ chip soc/intel/skylake
# PcieRpEnable: Enable root port
# PcieRpClkReqSupport: Enable CLKREQ#
# PcieRpClkReqNumber: Uses SRCCLKREQ2#
+ # PcieRpClkSrcNumber: Uses 2
# PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
# PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "2"
+ register "PcieRpClkSrcNumber[8]" = "2"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 50137896aa..a548ac98fd 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -157,6 +157,8 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
+ # RP 1 uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 22349d6984..3bcda3cc10 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -156,6 +156,8 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1"
# RP 1, Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[0]" = "1"
+ # RP 1 uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[0]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port