diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-12-04 12:17:24 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-12-06 18:23:55 +0000 |
| commit | 763b406107772ba57cf819fb12b9f3b78b9bf593 (patch) | |
| tree | 77ad534721f169ee9b34a9de5f9d52a2ad8d1409 /src/mainboard/google/poppy/variants/soraka/devicetree.cb | |
| parent | bea9b473d12f4c802eec78ef9cf7c5f5004e696a (diff) | |
mb/google/poppy/variants/soraka: Disable SPI TPM
Soraka is no longer using SPI TPM. This change disables GSPI0 in
device tree and updates gpio config accordingly.
Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/soraka/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 18 |
1 files changed, 2 insertions, 16 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 5e5a53730d..f71a1eb1d3 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -232,13 +232,6 @@ chip soc/intel/skylake }, }" - # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM - # communication before memory is up. - register "gspi[0]" = "{ - .speed_mhz = 1, - .early_init = 1, - }" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -247,7 +240,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, @@ -358,14 +351,7 @@ chip soc/intel/skylake device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" - device spi 0 on end - end - end # GSPI #0 + device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO |