diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2018-06-28 10:09:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-02 07:25:36 +0000 |
| commit | f86c3fc01746712acc0d3c79531eb12c80a2366c (patch) | |
| tree | b41862a9aa4bc8644885d7d0f0db39f2720ed694 /src/mainboard/google/poppy/variants/nocturne | |
| parent | 6459e427e8d59e7db23b2d7265205cd0b5a7d593 (diff) | |
nocturne: Do not set 4 LSB of SX9310 CRTL0
These bits start the acquisition process. They should only be set by the
driver.
BUG=b:74363445
TEST=compile
Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/27265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nocturne')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 09b7ef930a..17bd3c0eb4 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -305,7 +305,7 @@ chip soc/intel/skylake register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "0" - register "reg_prox_ctrl0" = "0x1a" + register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" register "reg_prox_ctrl3" = "0x0e" @@ -346,7 +346,7 @@ chip soc/intel/skylake register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "1" - register "reg_prox_ctrl0" = "0x1a" + register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" register "reg_prox_ctrl3" = "0x0e" |