diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2018-07-26 19:28:03 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-30 18:48:43 +0000 |
| commit | 4f9ff53e4239426d06c5a55a9e04b0e9a3e801cc (patch) | |
| tree | 370025fdc921902603f4245da83b0e6d888b2643 /src/mainboard/google/poppy/variants/nocturne/gpio.c | |
| parent | d091cd1fc16ec1daf058bd7b9d222f2e62ea8d75 (diff) | |
mb/google/poppy/variants/nocturne: enable FPMCU power
Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.
BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.
Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nocturne/gpio.c')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 3c186c7d8a..782ce00670 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = { /* A10 : CLKOUT_LPC1 ==> NC */ PAD_CFG_NC(GPP_A10), /* A11 : PCH_FP_PWR_EN */ - PAD_CFG_GPO(GPP_A11, 0, DEEP), + PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : ISH_GP6 */ PAD_CFG_NC(GPP_A12), /* A13 : SUSWARN# ==> SUSWARN_L */ @@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = { /* C9 : UART0_TXD ==> FPMCU_INT */ PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT), /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 0, DEEP), + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ |