diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-05-14 12:12:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-31 15:25:00 +0000 |
| commit | 405eb44fdb3a8a2d0188e2550367c846a76919aa (patch) | |
| tree | a5fb9f4f3892e67e45c1541a2af6d306356d8bc4 /src/mainboard/google/poppy/variants/nocturne/gpio.c | |
| parent | 9593e973fa0e3a104837d1df9659b3992d915b34 (diff) | |
mb/google/poppy/variants/nocturne: configure the FPMCU interface
The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.
We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.
BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.
Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/nocturne/gpio.c')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nocturne/gpio.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index bd38a20fdd..be76b64267 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -39,8 +39,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_A10), /* A11 : PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_A11, 0, DEEP), - /* A12 : FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_A12, NONE, DEEP), + /* A12 : ISH_GP6 */ + PAD_CFG_NC(GPP_A12), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -108,7 +108,7 @@ static const struct pad_config gpio_table[] = { /* B21 : GSPI1_MISO ==> PCH_FPMCU_SPI_MISO_R */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */ - PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* B23 : SM1ALERT# ==> PCHHOT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), @@ -129,13 +129,13 @@ static const struct pad_config gpio_table[] = { /* C7 : SM1DATA ==> NC */ PAD_CFG_NC(GPP_C7), /* C8 : UART0_RXD ==> PCH_FPMCU_BOOT0 */ - PAD_CFG_NC(GPP_C8), + PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> FPMCU_INT */ - PAD_CFG_NC(GPP_C9), + PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT), /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ - PAD_CFG_NC(GPP_C10), + PAD_CFG_GPO(GPP_C10, 0, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_NC(GPP_C11), + PAD_CFG_GPI_APIC_INVERT(GPP_C11, NONE, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ |