diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-05-01 15:47:06 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-05-03 00:29:31 +0200 |
| commit | 553f7fb27c14667e7bacf31040b9d58ca74dd06d (patch) | |
| tree | 78d56ed48eb925361da05d0de36c0bb7a49e55a8 /src/mainboard/google/poppy/variants/baseboard/gpio.c | |
| parent | a118c2edcca952628097e4ed3b4fd945c8d16e55 (diff) | |
mainboard/google/poppy: Add support for cr50 I2C TPM
1. Add support for using cr50 I2C TPM on poppy. This will not be
enabled until the next build.
2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding
Kconfig options are set.
BUG=b:36265511
TEST=Verified on a reworked board that I2C TPM communication works
fine.
Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/baseboard/gpio.c')
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/gpio.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index fcbbb1d554..2be9d0f86f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -92,6 +92,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ PAD_CFG_NC(GPP_B14), +#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -100,6 +101,16 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#else + /* B15 : GSPI0_CS# ==> NC */ + PAD_CFG_NC(GPP_B15), + /* B16 : GSPI0_CLK ==> NC */ + PAD_CFG_NC(GPP_B16), + /* B17 : GSPI0_MISO ==> NC */ + PAD_CFG_NC(GPP_B17), + /* B18 : GSPI0_MOSI ==> NC */ + PAD_CFG_NC(GPP_B18), +#endif /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS_L */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */ @@ -147,10 +158,17 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM) /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +#else + /* C18 : I2C1_SDA ==> NC */ + PAD_CFG_NC(GPP_C18), + /* C19 : I2C1_SCL ==> NC */ + PAD_CFG_NC(GPP_C19), +#endif /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ @@ -353,6 +371,7 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -361,11 +380,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#endif +#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM) /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +#endif /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ |