diff options
author | Caveh Jalali <caveh@google.com> | 2018-03-08 17:58:21 -0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-14 11:19:08 +0000 |
commit | 21df67ecd467c82f87ac80a658522c3fbf70a144 (patch) | |
tree | c08195b9479903490f593fd5fde4a9132d292a49 /src/mainboard/google/poppy/variants/baseboard/gpio.c | |
parent | 995d989ecbc7d17cf35ead1e5948b94eb22e1036 (diff) |
soc/intel/cannonlake: Disable RTC write protect
The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we
need this memory to be writable. We normally over-ride this in the
SoC chip init code, so we'll do the same on cannonlake.
BUG=b:71722386
BRANCH=none
TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip
all the bits.
Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/baseboard/gpio.c')
0 files changed, 0 insertions, 0 deletions