diff options
author | Furquan Shaikh <furquan@chromium.org> | 2017-04-14 22:11:13 -0700 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2017-04-19 19:18:32 +0200 |
commit | cbed0c26d0949489e7430013fd01c8f9ea1e3a88 (patch) | |
tree | 526de3c862432ef4641c906afac918ca6cb498e4 /src/mainboard/google/poppy/spd | |
parent | 374d1ff8aacba5fc872b76bed6daf97da55e997a (diff) |
mainboard/google/poppy: Provide memory configuration variant API
Add support for memory configuration by providing weak implementation
from the baseboard. All SPD files are present under spd/
directory. SPD_SOURCES must be provided by the variants to ensure that
required SPD hex files are included in the SPD binary.
BUG=b:37375693
Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19325
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/poppy/spd')
-rw-r--r-- | src/mainboard/google/poppy/spd/Makefile.inc | 31 | ||||
-rw-r--r-- | src/mainboard/google/poppy/spd/spd.c | 116 | ||||
-rw-r--r-- | src/mainboard/google/poppy/spd/spd.h | 35 |
3 files changed, 5 insertions, 177 deletions
diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc index 2a3c0c0803..30e632ded0 100644 --- a/src/mainboard/google/poppy/spd/Makefile.inc +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -1,32 +1,11 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 Google Inc. -## Copyright (C) 2016 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b0000 -SPD_SOURCES += empty # 0b0001 -SPD_SOURCES += empty # 0b0010 -SPD_SOURCES += micron_dimm_MT52L512M64D4PQ-107 # 0b0011 -SPD_SOURCES += hynix_dimm_H9CCNNNCPTALBR-NUD # 0b0100 -SPD_SOURCES += micron_dimm_MT52L1G64D8QC-107 # 0b0101 -SPD_SOURCES += hynix_dimm_H9CCNNNFAGMLLR-NUD # 0b0110 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif # Include spd ROM data $(SPD_BIN): $(SPD_DEPS) diff --git a/src/mainboard/google/poppy/spd/spd.c b/src/mainboard/google/poppy/spd/spd.c deleted file mode 100644 index fa0012a908..0000000000 --- a/src/mainboard/google/poppy/spd/spd.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <string.h> - -#include <variant/gpio.h> -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -uintptr_t mainboard_get_spd_data(void) -{ - char *spd_file; - size_t spd_file_len; - int spd_index; - - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); - spd_index = 1; - } - - spd_index *= SPD_LEN; - mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); - - return (uintptr_t)(spd_file + spd_index); -} diff --git a/src/mainboard/google/poppy/spd/spd.h b/src/mainboard/google/poppy/spd/spd.h deleted file mode 100644 index 4195a0cf1b..0000000000 --- a/src/mainboard/google/poppy/spd/spd.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc. - * Copyright (C) 2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 - -uintptr_t mainboard_get_spd_data(void); - -#endif |