exynos5420: Make USB A-A booting work with early data cache

Apparently the IROM doesn't like data caches... the recently added
dcache-in-bootblock makes A-A booting fail, and flushes/invalidations
alone don't seem to fix it. It's pretty fast anyway, so we just disable
the cache again for the duration of the IROM call.

Also removes a superfluous invalidation line from the bootblock code...
dcache_mmu_enable/disable already take care of that.

Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66602
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f)

exynos5: Implement booting from SDMMC media

This patch augments the alternative CBFS media source implementation for
Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as
an SD or uSD card reader, if available). It also moves MMC
initialization for the Snow, Pit and Kirby boards from romstage to
ramstage (mainboard_init) to prevent it from interfering with the IROM
during SDMMC boot.

Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66154
(cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc)

snow and pit: turn on FET4 (for SD card) at bootup

Explictly enable FET4 on Snow and Pit.

Historically we haven't needed to do this because:
* On snow there's a bypass around FET4 which effectively eliminates
  it.  Even if we don't turn on FET4 the SD card is still powered.
  Turning on FET4 doesn't hurt though and is technically correct.
* On pit the EC turns on FET4 on cold bootup.

On pit we run into a problem if the kernel turns off FET4 like in
<https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a
software reset or warm reset.  In this case the EC won't know to turn
it back on.

This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c
Reviewed-on: https://gerrit.chromium.org/gerrit/66786
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646)

Squashed three commits for alternate cbfs SD support.

Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6530
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 22 insertions, 15 deletions

diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 3ffb824216..9aa8d5cd30 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -330,6 +330,19 @@ static void disable_usb30_pll(void)
 	gpio_direction_output(usb3_pll_l, 0);
 }
 
+static void setup_storage(void)
+{
+	/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
+	if (clock_set_dwmci(PERIPH_ID_SDMMC0))
+		printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
+	exynos_pinmux_sdmmc0();
+
+	/* MMC2: Removable, 4 bit mode, no GPIO. */
+	/* (Must be after romstage to avoid breaking SDMMC boot.) */
+	clock_set_dwmci(PERIPH_ID_SDMMC2);
+	exynos_pinmux_sdmmc2();
+}
+
 static void gpio_init(void)
 {
 	/* Set up the I2C busses. */
@@ -370,6 +383,12 @@ static void backlight_vdd(void)
 	tps65090_thru_ec_fet_set(1);
 }
 
+static void sdmmc_vdd(void)
+{
+	/* Enable FET4, P3.3V_SDCARD */
+	tps65090_thru_ec_fet_set(4);
+}
+
 /* this happens after cpu_init where exynos resources are set */
 static void mainboard_init(device_t dev)
 {
@@ -380,6 +399,7 @@ static void mainboard_init(device_t dev)
 	void *fb_addr = (void *)(get_fb_base_kb() * KiB);
 
 	gpio_init();
+	setup_storage();
 	tmu_init(&exynos5420_tmu_info);
 
 	/* Clock Gating all the unused IP's to save power */
@@ -388,6 +408,8 @@ static void mainboard_init(device_t dev)
 	/* Disable USB3.0 PLL to save 250mW of power */
 	disable_usb30_pll();
 
+	sdmmc_vdd();
+
 	set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
 
 	/*
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 319ebf97e2..7967a559f2 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -40,8 +40,6 @@
 #include <drivers/maxim/max77802/max77802.h>
 #include <device/i2c.h>
 
-#define MMC0_GPIO_PIN	(58)
-
 #define PMIC_I2C_BUS	4
 
 struct pmic_write
@@ -109,18 +107,6 @@ static int setup_power(int is_resume)
 	return error;
 }
 
-static void setup_storage(void)
-{
-	/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
-	if (clock_set_dwmci(PERIPH_ID_SDMMC0))
-		printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
-	exynos_pinmux_sdmmc0();
-
-	/* MMC2: Removable, 4 bit mode, no GPIO. */
-	clock_set_dwmci(PERIPH_ID_SDMMC2);
-	exynos_pinmux_sdmmc2();
-}
-
 static void setup_ec(void)
 {
 	/* SPI2 (EC) is slower and needs to work in half-duplex mode with
@@ -270,7 +256,6 @@ void main(void)
 		wakeup();
 	}
 
-	setup_storage();
 	setup_gpio();
 	setup_ec();