diff options
author | Shawn Nematbakhsh <shawnn@chromium.org> | 2013-05-28 17:46:49 -0700 |
---|---|---|
committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-02 18:04:52 +0100 |
commit | 6fb41dcad7e5030530f307b1ed86ffecd5e6eb89 (patch) | |
tree | d932151ff5ce5455fe2255491319c85519fede4c /src/mainboard/google/peppy/romstage.c | |
parent | 0bf1febed82c8433686978c74a0c851d85189f91 (diff) |
peppy: Update GPIO table + USB port map.
- Update GPIO table to match board.
- Update USB port map.
- Remove iSSD power sequencing code.
Change-Id: Iaa8e5921ed9db6bcfd18b5a888c7f80b2c93a710
Reviewed-on: https://gerrit.chromium.org/gerrit/56869
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4211
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/google/peppy/romstage.c')
-rw-r--r-- | src/mainboard/google/peppy/romstage.c | 46 |
1 files changed, 5 insertions, 41 deletions
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index d979203572..b172da2cf3 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -98,39 +98,6 @@ static void copy_spd(struct pei_data *peid) sizeof(peid->spd_data[0])); } -/* - * Power Sequencing for SanDisk i100/i110 SSD - * - * Must be sequenced in this order with specified timing. - * - * 1. VCC_IO : 30us - 100ms - * 2. VCC_FLASH : 70us - 10ms - * 3. VCCQ : 70us - 10ms - * 4. VDDC : 30us - 100ms - * - * There is no feedback to know if the voltage has stabilized - * so this implementation will use the max ramp times. That - * means it adds significantly to the boot time. - */ -static void issd_power_sequence(void) -{ - struct gpio_seq { - int gpio; - int wait_ms; - } issd_gpio_seq[] = { - { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ - { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ - { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ - { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ - }; - int step; - - for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) { - set_gpio(issd_gpio_seq[step].gpio, 1); - udelay(issd_gpio_seq[step].wait_ms * 1000); - } -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { @@ -161,18 +128,18 @@ void mainboard_romstage_entry(unsigned long bist) usb2_ports: { /* Length, Enable, OCn# */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ + { 0x0040, 1, 0 }, /* P1: Port A */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ - { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ + { 0x0040, 1, 2 }, /* P4: USB 2.0 Port */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ }, usb3_ports: { /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN6 */ + { 1, 0 }, /* P1; Port A, CN6 */ + { 0, USB_OC_PIN_SKIP }, /* P2; */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }, @@ -188,7 +155,4 @@ void mainboard_romstage_entry(unsigned long bist) /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); - - /* Power sequence the iSSD module */ - issd_power_sequence(); } |