SNB+MRC boards: Migrate MRC settings to devicetree

For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.

Some exceptions allowed are described below and in code comments.

SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.

google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.

TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.

Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

2 files changed, 24 insertions, 41 deletions

diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index 6bc4b454d6..bf1bff36f2 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -17,7 +17,25 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x000001d4"
 	register "gpu_pch_backlight" = "0x03aa0000"
 
-	register "max_mem_clock_mhz" = "666"
+	register "ec_present" = "1"
+	# FIXME: Native raminit requires reduced max clock
+	register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+	register "usb_port_config" = "{
+		{ 0, 3, 0x0000 },
+		{ 1, 0, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 0, 3, 0x0000 },
+		{ 0, 3, 0x0000 },
+		{ 0, 3, 0x0000 },
+		{ 0, 3, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },}"
 
 	device domain 0 on
 		device ref host_bridge on end # host bridge
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index ba93531cb5..efdb9a2fea 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -52,46 +52,11 @@ void mainboard_late_rcba_config(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* Empty and onboard Ports 0-7, set to un-used pin OC3 */
-			{ 0, 3, 0x0000 }, /* P0: Empty */
-			{ 1, 0, 0x0040 }, /* P1: Left USB 1  (OC0) */
-			{ 1, 1, 0x0040 }, /* P2: Left USB 2  (OC1) */
-			{ 1, 1, 0x0040 }, /* P3: Left USB 3  (OC1) */
-			{ 0, 3, 0x0000 }, /* P4: Empty */
-			{ 0, 3, 0x0000 }, /* P5: Empty */
-			{ 0, 3, 0x0000 }, /* P6: Empty */
-			{ 0, 3, 0x0000 }, /* P7: Empty */
-			/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
-			{ 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */
-			{ 0, 4, 0x0000 }, /* P9: Empty */
-			{ 1, 4, 0x0040 }, /* P10: Camera (no OC) */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 0, 4, 0x0000 }, /* P12: Empty */
-			{ 0, 4, 0x0000 }, /* P13: Empty */
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {