diff options
author | Vladimir Serbinenko <phcoder@gmail.com> | 2016-02-10 01:36:25 +0100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-02-12 04:20:57 +0100 |
commit | ffbb3c0b8abea621eb7a1583d630cf06c8cbfbbc (patch) | |
tree | 9a45adcee57358dd8ebafc4201db2cbd0beef679 /src/mainboard/google/parrot/romstage.c | |
parent | 622eea7e815af39dbee290eddc487baab5e8a5f5 (diff) |
Merge sandy/ivybridge romstage flow for MRC and non-MRC.
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/parrot/romstage.c')
-rw-r--r-- | src/mainboard/google/parrot/romstage.c | 98 |
1 files changed, 15 insertions, 83 deletions
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 029805b045..60c3f010f8 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -31,7 +31,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" @@ -39,7 +38,7 @@ #include <tpm.h> #include "ec/compal/ene932/ec.h" -static void pch_enable_lpc(void) +void pch_enable_lpc(void) { /* Parrot EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ @@ -52,7 +51,7 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001); } -static void rcba_config(void) +void rcba_config(void) { u32 reg32; @@ -107,13 +106,13 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_early_init(int s3resume) { - int boot_mode = 0; - int cbmem_was_initted; +} - struct pei_data pei_data = { +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -158,81 +157,14 @@ void main(unsigned long bist) { 0, 4, 0x0000 }, /* P13: Empty */ }, }; + *pei_data = pei_data_template; +} - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&parrot_gpio_map); - - /* Initialize console device(s) */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected\n"); - boot_mode = 1; - - /* System is not happy after keyboard reset... */ - printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - sandybridge_early_initialization(SANDYBRIDGE_MOBILE); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - - boot_mode = southbridge_detect_s3_resume() ? 2 : 0; - - post_code(0x38); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x39); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(&pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3c); - - rcba_config(); - post_code(0x3d); - - quick_ram_check(); - post_code(0x3e); - - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); - - if (boot_mode==2 && !cbmem_was_initted) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); - } - northbridge_romstage_finalize(boot_mode==2); +void mainboard_config_superio(void) +{ +} - post_code(0x3f); - if (CONFIG_LPC_TPM) { - init_tpm(boot_mode == 2); - } +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; } |