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| author | Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> | 2021-06-04 10:35:15 -0500 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-06-07 16:04:36 +0000 |
| commit | 177a402b6eb554cf3ad1dce12bc558582877cba3 (patch) | |
| tree | 5ed7f628bb62f8b123d851bee87049ae915ce034 /src/mainboard/google/parrot/gpio.c | |
| parent | 0889a80c6300db1d39f00e0650cef48f99ccbf70 (diff) | |
soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.
BUG=b:190153208
Cq-depend: chrome-internal:3889619
TEST=verify HOB is present and correct size (13) is reported
Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/parrot/gpio.c')
0 files changed, 0 insertions, 0 deletions