diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-11-24 09:19:56 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-26 11:19:52 +0000 |
| commit | 9234d9231b177c80281805301d4c67c8ca4d02bb (patch) | |
| tree | 797e9b771e74e039ca0c9da504099e8851d3dd28 /src/mainboard/google/parrot/dsdt.asl | |
| parent | 40713aaa4347ba0b3fac591b8f1f5b437c6b2ca4 (diff) | |
ec/google/chromeec: Support 5 temperature sensors
Some boards with the chrome EC will need to support more than 4
temperature sensors, so modify the number of TSRs supported when
generating the ACPI code. Note that the EC memory map already has
support for up to 16 TSRs, so no change is required on the EC
side.
BUG=b:207585491
TEST=with previous patch and some test data in brya0 overridetree.cb,
dump the SSDT and verify that all of the existing Methods for TSR0-TSR3
are also added for TSR4, as well as all Notify, etc.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59633
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/parrot/dsdt.asl')
0 files changed, 0 insertions, 0 deletions