diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-14 16:31:25 +1000 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-18 07:42:27 +0200 |
| commit | 1f9653a1bc737587deed507cd173595b180aad8f (patch) | |
| tree | ee27277067933d1b8bd6d88336f0d29860439905 /src/mainboard/google/panther | |
| parent | d5339ae0b73b46f65c1d88fd4066a0e98f09b6b3 (diff) | |
src/superio/ite/it8772f: Separate mainboard from SIO at obj level
Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.
Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/panther')
| -rw-r--r-- | src/mainboard/google/panther/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c367968f90..c90c8e7987 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -30,11 +30,11 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" #include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/it8772f/early_serial.c" #include "superio/ite/common/ite.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define DUMMY_DEV PNP_DEV(0x2e, 0) const struct rcba_config_instruction rcba_config[] = { @@ -145,7 +145,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Early SuperIO setup */ ite_kill_watchdog(GPIO_DEV); - it8772f_ac_resume_southbridge(); + it8772f_ac_resume_southbridge(DUMMY_DEV); pch_enable_lpc(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |