diff options
| author | John Zhao <john.zhao@intel.com> | 2021-10-04 09:15:36 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-29 16:53:57 +0000 |
| commit | b1700805ef121836a847668b68673f1560a90722 (patch) | |
| tree | 909a6546e0a9b03aaf7882bccdc08697df8d4c4d /src/mainboard/google/octopus | |
| parent | 287cc02c007fd47b515d19389ea00ea0461fd5a1 (diff) | |
soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization
The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology which has the same implementation on Tiger Lake in
commit I5a19118b75ed0a78b7436f2f90295c03928300d7.
BUG=b:199757442
TEST= It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Alder Lake platform boards.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0c8977c96de27ab0e554469eba658660975b8493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/octopus')
0 files changed, 0 insertions, 0 deletions