mb, soc/intel: Reorganize CNVi device entries in devicetree

This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.

Before:
chip drivers/wifi/generic
	register "wake" = "..."
	device pci xx.y on end
end

After:
device pci xx.y on
	chip drivers/wifi/generic
		register "wake" = "..."
		device generic 0 on end
	end
end

Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

1 files changed, 6 insertions, 4 deletions

diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 6d77116c89..cbcd48aab4 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -114,10 +114,12 @@ chip soc/intel/apollolake
 		device pci 00.2 off end	# - NPK
 		device pci 02.0 on  end	# - Gen
 		device pci 03.0 on  end # - Gaussian Mixture Model (GMM)
-		chip drivers/wifi/generic
-			register "wake" = "GPE0A_CNVI_PME_STS"
-			device pci 0c.0 on  end	# - CNVi
-		end
+		device pci 0c.0 on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0A_CNVI_PME_STS"
+				device generic 0 on end
+			end
+		end	# - CNVi
 		device pci 0d.0 on  end	# - P2SB
 		device pci 0d.1 on  end	# - PMC
 		device pci 0d.2 on  end	# - Fast SPI