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authorKevin Chiu <Kevin.Chiu@quantatw.com>2020-10-19 14:16:48 +0800
committerFelix Held <felix-coreboot@felixheld.de>2020-10-24 14:00:08 +0000
commitd3318cfe498bf53d8ce7d1cd55afad4a93705216 (patch)
tree7124e5a55a51ce87d7bc6a4c4bc72a4741cf29da /src/mainboard/google/octopus
parent062b92ef654a97648380a1a9a9fe34229ee76e31 (diff)
mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of "HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers. COMPDISTUNE0: 0x3->0x7 TXVREFTUNE0: 0x6->0xf BUG=b:166398726 BRANCH=zork TEST=1. emerge-zork coreboot 2. check U2 register is set correctly. 3. U2 SI all pass Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46545 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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