diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2018-12-05 15:10:30 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-12-19 15:59:39 +0000 |
| commit | d652a92a6a9e846347e5a97bf2f986b09b9b7d2f (patch) | |
| tree | b3ed2860db789f9155cff4b780b9dc881d43aee3 /src/mainboard/google/octopus/variants | |
| parent | 817994c1bec48733679c34fe717a07ad81af18ac (diff) | |
mb/google/octopus: Override emmc DLL values for Yorp
New emmc DLL values for Yorp.
BUG=b:120561055
BRANCH=octopus
TEST=Boot to OS, chromeos-install, mmc_test
Change-Id: I771c959a15959160224f056c0a16aa65bfbba94e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/mainboard/google/octopus/variants')
| -rw-r--r-- | src/mainboard/google/octopus/variants/yorp/overridetree.cb | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/yorp/overridetree.cb b/src/mainboard/google/octopus/variants/yorp/overridetree.cb index de711bae08..8d4cd15003 100644 --- a/src/mainboard/google/octopus/variants/yorp/overridetree.cb +++ b/src/mainboard/google/octopus/variants/yorp/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0A12" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00195959" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10025" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid |