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authorTony Huang <tony-huang@quanta.corp-partner.google.com>2019-03-08 14:13:45 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-14 11:27:34 +0000
commitfa861eea3057bbbf067c7361c35721a2681a036e (patch)
treea15fb48e840d5df411dfe1c9d7ab1c570ca197a4 /src/mainboard/google/octopus/variants/bloog/overridetree.cb
parent59bd2318dd6278444942f8d353675d43d14d7d16 (diff)
mb/google/octopus: Create Bloog variant
This commit create bloog variant for Octopus. Initial settings are copy from meep. Remove I2C tuning, WACOM digitizer and WEIDA touchscreen. Override GPIO configuration for unused LTE and Pen. BUG=b:127736039 BRANCH=octopus TEST=None Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/octopus/variants/bloog/overridetree.cb')
-rw-r--r--src/mainboard/google/octopus/variants/bloog/overridetree.cb109
1 files changed, 109 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb
new file mode 100644
index 0000000000..20b5dd3b71
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb
@@ -0,0 +1,109 @@
+chip soc/intel/apollolake
+
+ # EMMC Tx CMD Delay
+ # Refer to EDS-Vol2-16.32.
+ # [14:8] steps of delay for DDR mode, each 125ps.
+ # [6:0] steps of delay for SDR mode, each 125ps.
+ register "emmc_tx_cmd_cntl" = "0x505"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-16.33.
+ # [14:8] steps of delay for HS400, each 125ps.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps.
+ register "emmc_tx_data_cntl1" = "0x0b0d"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-16.34.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_tx_data_cntl2" = "0x1c2a2a2a"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-16.35.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_rx_cmd_data_cntl1" = "0x00171a1a"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-16.37.
+ # [17:16] stands for Rx Clock before Output Buffer
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+ # [6:0] steps of delay for HS200, each 125ps.
+ register "emmc_rx_cmd_data_cntl2" = "0x10028"
+
+ # EMMC Rx Strobe Delay
+ # Refer to EDS-Vol2-16.36.
+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
+ register "emmc_rx_strobe_cntl" = "0x0b0b"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ }"
+
+ device domain 0 on
+ device pci 16.0 off end # - I2C 0
+ device pci 17.1 on
+ chip drivers/i2c/da7219
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
+ register "btn_cfg" = "50"
+ register "mic_det_thr" = "500"
+ register "jack_ins_deb" = "20"
+ register "jack_det_rate" = ""32ms_64ms""
+ register "jack_rem_deb" = "1"
+ register "a_d_btn_thr" = "0xa"
+ register "d_b_btn_thr" = "0x16"
+ register "b_c_btn_thr" = "0x21"
+ register "c_mic_btn_thr" = "0x3e"
+ register "btn_avg" = "4"
+ register "adc_1bit_rpt" = "1"
+ register "micbias_lvl" = "2600"
+ register "mic_amp_in_sel" = ""diff""
+ device i2c 1a on end
+ end
+ end # - I2C 5
+ device pci 17.2 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
+ register "wake" = "GPE0_DW3_27"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end # - I2C 6
+ device pci 17.3 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
+ register "reset_delay_ms" = "20"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
+ register "enable_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ device i2c 10 on end
+ end
+ end # - I2C 7
+ end
+
+ # Disable compliance mode
+ register "DisableComplianceMode" = "1"
+end