diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2018-06-29 23:27:40 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-07-18 20:42:33 +0000 |
| commit | ebde6595035a960e25ab74bdcfffaed45d16e7a6 (patch) | |
| tree | 7b416055f4f5f6a60dec686383260370381b4302 /src/mainboard/google/octopus/variants/baseboard/devicetree.cb | |
| parent | e577168ae3163768bc76d23e4e121a57b436abd6 (diff) | |
mb/google/octopus/variants/baseboard: Udpate CPU critical temp
Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
busty workloads like Octane, Aquarium on open yorp board with heat sink,
sometime CPU temperature spikes till 99 degree Celsius and DPTF
initiates system shutdown. With reference to previous APL/reef/coral
platforms, this updates 105 degree Celsius for the CPU critical
temperature trip value to avoid shutdown. This patch also updates power
limit1 value to avoid the abrupt thermal shutdown by DPTF.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Icd786d3c9b5f7c733dac3fd3e22579e2434058a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/octopus/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 6f71f169d4..9cab69c167 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -42,10 +42,11 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_95_64" register "gpe0_dw3" = "PMC_GPE_N_63_32" - # PL1 override 12000 mW: Due to error in the energy calculation for + # PL1 override 8000 mW: Due to error in the energy calculation for # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" + # be reached when RAPL PL1 is set to 8W. + # TODO: Need to tune this value on closed chassis system. + register "tdp_pl1_override_mw" = "8000" # Set RAPL PL2 to 15W. register "tdp_pl2_override_mw" = "15000" |