diff options
author | Hannah Williams <hannah.williams@intel.com> | 2018-02-09 18:35:17 -0800 |
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committer | Martin Roth <martinroth@google.com> | 2018-02-15 21:38:50 +0000 |
commit | 5e83e8b130a7072fd62b581f260545689dcf73fc (patch) | |
tree | d77ecbe5e08392939ae03491c4d738e3c9458966 /src/mainboard/google/octopus/smihandler.c | |
parent | af15268c103642f32461d939cc4a9b836ad8db94 (diff) |
mb/google/octopus: Add new board
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.
Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/octopus/smihandler.c')
-rw-r--r-- | src/mainboard/google/octopus/smihandler.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c new file mode 100644 index 0000000000..59ac217bbd --- /dev/null +++ b/src/mainboard/google/octopus/smihandler.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <soc/pm.h> +#include <soc/gpio.h> +#include <variant/ec.h> +#include <variant/gpio.h> + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ + if (gpi_status_get(sts, EC_SMI_GPI)) + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(&num); + gpio_configure_pads(pads, num); + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} |