diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2018-02-09 18:35:17 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-15 21:38:50 +0000 |
| commit | 5e83e8b130a7072fd62b581f260545689dcf73fc (patch) | |
| tree | d77ecbe5e08392939ae03491c4d738e3c9458966 /src/mainboard/google/octopus/dsdt.asl | |
| parent | af15268c103642f32461d939cc4a9b836ad8db94 (diff) | |
mb/google/octopus: Add new board
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.
Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/octopus/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/octopus/dsdt.asl | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl new file mode 100644 index 0000000000..c921df91b3 --- /dev/null +++ b/src/mainboard/google/octopus/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/ec.h> +#include <variant/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +} |