diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2017-02-14 10:48:11 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-04-24 22:33:06 +0200 |
| commit | c77259c4e5e02fcf829afe9bf437b70dbddcbf3c (patch) | |
| tree | 231a90a203c33e3210c7d40c9c208131b76aa328 /src/mainboard/google/oak/bootblock.c | |
| parent | 50340f5480c943b6434c9b5e6178731a9977cae3 (diff) | |
google/oak: Support cr50 over I2C on rowan
This patch enables TPM2 using cr50 over I2C for the Rowan board, and
adds an mt8173 specific TPM IRQ polling function. The function relies on
the appropriate EINT input configured to trigger the ready status on
the rising edge.
The cr50 TPM is on I2C address 0x50.
The cr50 interrupt GPIO is also made available for use by depthcharge
via the coreboot tables.
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19364
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak/bootblock.c')
| -rw-r--r-- | src/mainboard/google/oak/bootblock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 04a3a550ec..fe9c9ba8c4 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -88,6 +88,9 @@ void bootblock_mainboard_init(void) /* Init i2c bus 2 Timing register for TPM */ mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS); + if (IS_ENABLED(CONFIG_OAK_HAS_TPM2)) + gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); setup_chromeos_gpios(); |