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authorVadim Bendebury <vbendeb@chromium.org>2017-02-14 10:48:11 +0800
committerAaron Durbin <adurbin@chromium.org>2017-04-24 22:33:06 +0200
commitc77259c4e5e02fcf829afe9bf437b70dbddcbf3c (patch)
tree231a90a203c33e3210c7d40c9c208131b76aa328 /src/mainboard/google/oak/Kconfig
parent50340f5480c943b6434c9b5e6178731a9977cae3 (diff)
google/oak: Support cr50 over I2C on rowan
This patch enables TPM2 using cr50 over I2C for the Rowan board, and adds an mt8173 specific TPM IRQ polling function. The function relies on the appropriate EINT input configured to trigger the ready status on the rising edge. The cr50 TPM is on I2C address 0x50. The cr50 interrupt GPIO is also made available for use by depthcharge via the coreboot tables. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19364 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak/Kconfig')
-rw-r--r--src/mainboard/google/oak/Kconfig9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig
index 28771b8dd7..d727ffca92 100644
--- a/src/mainboard/google/oak/Kconfig
+++ b/src/mainboard/google/oak/Kconfig
@@ -18,6 +18,12 @@ config BOARD_GOOGLE_OAK_COMMON
if BOARD_GOOGLE_OAK_COMMON
+config OAK_HAS_TPM2
+ bool
+ default y if BOARD_GOOGLE_ROWAN
+ default n
+ select MAINBOARD_HAS_I2C_TPM_CR50
+
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_MEDIATEK_MT8173
@@ -56,7 +62,8 @@ config DRIVER_TPM_I2C_BUS
config DRIVER_TPM_I2C_ADDR
hex
- default 0x20
+ default 0x20 if !OAK_HAS_TPM2
+ default 0x50 if OAK_HAS_TPM2
config BOOT_DEVICE_SPI_FLASH_BUS
int