diff options
| author | Gabe Black <gabeblack@google.com> | 2014-03-01 03:27:00 -0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-13 06:24:19 +0100 |
| commit | b9a4b713f88c111628d3b35d8a695de88ff39ecd (patch) | |
| tree | 8443e6c17be425daeed056166c46cfada5d58d4f /src/mainboard/google/nyan_big/romstage.c | |
| parent | c1e41b7215537f0da79874ec144693bf20a60162 (diff) | |
nyan: nyan_big: Mark the address range covering the SRAM as cachable.
The SRAM is very likely faster than going all the way out to DRAM for data,
but I don't think it's part of the cores themselves and won't be as fast as
the L1 caches. Enabling caching for this region reduces the time it takes to
get to the payload by about 75% when serial output is disabled and the main
part of display init is commented out.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan.
BRANCH=None
Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/188459
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e
Reviewed-on: http://review.coreboot.org/7407
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/google/nyan_big/romstage.c')
| -rw-r--r-- | src/mainboard/google/nyan_big/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 0fbe316882..51f5a49264 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -89,10 +89,16 @@ static void __attribute__((noinline)) romstage(void) u32 dram_size = dram_end - dram_start; mmu_init(); + /* Device memory below DRAM is uncached. */ mmu_config_range(0, dram_start, DCACHE_OFF); + /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ + mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); + /* DRAM is cached. */ mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + /* A window for DMA is uncached. */ mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + /* The space above DRAM is uncached. */ if (dram_end < 4096) mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); mmu_disable_range(0, 1); |