diff options
| author | Ken Chang <kenc@nvidia.com> | 2014-04-22 12:55:00 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-17 20:49:02 +0100 |
| commit | 5a056d30a1fd609994e0a9aa70f5788c68e3a785 (patch) | |
| tree | 95e72b64769bdcd741a694555ff72b5c99991d79 /src/mainboard/google/nyan | |
| parent | 41359bd230942bea9cea234e147e629a78cbf794 (diff) | |
tegra124: modify panel init sequence
Panel datasheet defines some delay between PWM signal out and
backlight enable. This change fixes the current sequence
and makes the delays adjustable by dt setting.
BRANCH=none
BUG=chrome-os-partner:28008
TEST=Verified on Big DVT and Nyan/Norrin panels.
Panel works fine with dev mode, and the measurement
of power on sequence meets panel requirements.
Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/196183
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3
Reviewed-on: http://review.coreboot.org/7776
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/nyan')
| -rw-r--r-- | src/mainboard/google/nyan/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index 885445022e..e7ae54d52b 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -47,6 +47,7 @@ chip soc/nvidia/tegra124 # various panel delay time register "vdd_delay_ms" = "200" + register "pwm_to_bl_delay_ms" = "10" register "vdd_to_hpd_delay_ms" = "200" register "hpd_unplug_min_us" = "2000" register "hpd_plug_min_us" = "250" |