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authorShaunak Saha <shaunak.saha@intel.com>2020-09-02 15:37:00 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-10-23 20:25:49 +0000
commit0d0f43f9d36f3a942322486b486b98f7ae5cd70d (patch)
tree1010a58c535b9d3979cbc43cb55906cd66cebd2a /src/mainboard/google/nyan
parent7fa445e385cae66f8c696fb54cbd38dff49452c8 (diff)
soc/intel/tigerlake: Add Acoustic features
Expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRateFor BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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