google/ninja: Upstream AOpen Chromebox Commerical

Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to
upstream, using google/rambi as a reference.

original source:
branch firmware-ninja-5216.383.B
commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA]

TEST=built and booted Linux on ninja with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)

Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/14950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

34 files changed, 2229 insertions, 0 deletions

diff --git a/src/mainboard/google/ninja/Kconfig b/src/mainboard/google/ninja/Kconfig
new file mode 100644
index 0000000000..232b75d3d0
--- /dev/null
+++ b/src/mainboard/google/ninja/Kconfig
@@ -0,0 +1,50 @@
+if BOARD_GOOGLE_NINJA
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_INTEL_BAYTRAIL
+	select EC_GOOGLE_CHROMEEC
+	select ENABLE_BUILTIN_COM1
+	select DRIVERS_UART_8250IO
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
+
+config CHROMEOS
+	select EC_SOFTWARE_SYNC
+	select VIRTUAL_DEV_SWITCH
+	select PHYSICAL_REC_SWITCH
+
+config MAINBOARD_DIR
+	string
+	default google/ninja
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Ninja"
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0f31.rom"
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config HAVE_ME_BIN
+	bool
+	default n
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+	string
+	default ""
+
+config GBB_HWID
+	string
+	depends on CHROMEOS
+	default "NINJA TEST A-A 0653"
+
+endif # BOARD_GOOGLE_NINJA
diff --git a/src/mainboard/google/ninja/Kconfig.name b/src/mainboard/google/ninja/Kconfig.name
new file mode 100644
index 0000000000..17ed8dbb62
--- /dev/null
+++ b/src/mainboard/google/ninja/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_NINJA
+	bool "Ninja"
diff --git a/src/mainboard/google/ninja/Makefile.inc b/src/mainboard/google/ninja/Makefile.inc
new file mode 100644
index 0000000000..1c21aaede2
--- /dev/null
+++ b/src/mainboard/google/ninja/Makefile.inc
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += gpio.c
+ramstage-y += irqroute.c
+ramstage-y += w25q64.c
+ramstage-y += lan.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/google/ninja/acpi/chromeos.asl b/src/mainboard/google/ninja/acpi/chromeos.asl
new file mode 100644
index 0000000000..814380c763
--- /dev/null
+++ b/src/mainboard/google/ninja/acpi/chromeos.asl
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Fields are in the following order.
+ * - Type: recovery = 1 developer mode = 2 write protect = 3
+ * - Active Level - if -1 not a valid gpio
+ * - GPIO number encoding - if -1 not a valid gpio
+ * - Chipset Name
+ *
+ * Note: On Bay Trail we need to encode gpios within the 3 separate banks
+ * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
+ * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
+ */
+
+Name(OIPG, Package() {
+	Package () { 0x0001, 0, 0x2008, "BayTrail" }, // recovery
+	Package () { 0x0003, 1, 0x2006, "BayTrail" }, // firmware write protect
+})
diff --git a/src/mainboard/google/ninja/acpi/dptf.asl b/src/mainboard/google/ninja/acpi/dptf.asl
new file mode 100644
index 0000000000..be9bd657df
--- /dev/null
+++ b/src/mainboard/google/ninja/acpi/dptf.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	105
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	80
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	80
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Effect on Temp Sensor 1 */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		// Revision
+	Package () {	// Power Limit 1
+		0,	// PowerLimitIndex, 0 for Power Limit 1
+		1600,	// PowerLimitMinimum
+		6200,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		200	// StepSize
+	},
+	Package () {	// Power Limit 2
+		1,	// PowerLimitIndex, 1 for Power Limit 2
+		8000,	// PowerLimitMinimum
+		8000,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		1000	// StepSize
+	}
+})
+
+/* Include Baytrail DPTF */
+#include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/ninja/acpi/ec.asl b/src/mainboard/google/ninja/acpi/ec.asl
new file mode 100644
index 0000000000..147b67d6de
--- /dev/null
+++ b/src/mainboard/google/ninja/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/ninja/ec.h>
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/ninja/acpi/mainboard.asl b/src/mainboard/google/ninja/acpi/mainboard.asl
new file mode 100644
index 0000000000..513fe7d290
--- /dev/null
+++ b/src/mainboard/google/ninja/acpi/mainboard.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/ninja/onboard.h>
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+		Name (_PRW, Package() { BOARD_PCH_WAKE_GPIO, 0x5 })
+		Method (_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+		Name (_UID, 1)
+	}
+}
+
+Scope (\_SB.I2C2)
+{
+	Device (CODC)
+	{
+		/*
+		 * TODO(dlaurie): Need official HID.
+		 *
+		 * The current HID is created from the Maxim Integrated
+		 * PCI Vendor ID 193Ch and a shortened device identifier.
+		 */
+		Name (_HID, "193C9890")
+		Name (_DDN, "Maxim 98090 Codec")
+		Name (_UID, 1)
+
+		Name (SPKR, 0)
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x10,                     // SlaveAddress
+				ControllerInitiated,      // SlaveMode
+				400000,                   // ConnectionSpeed
+				AddressingMode7Bit,       // AddressingMode
+				"\\_SB.I2C2",             // ResourceSource
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_CODEC_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S2EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+	}
+}
+
+Scope (\_SB.LPEA)
+{
+	Name (GBUF, ResourceTemplate ()
+	{
+		/* Jack Detect (index 0) */
+		GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+			 "\\_SB.GPSC") { 14 }
+
+		/* Mic Detect (index 1) */
+		GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+			 "\\_SB.GPSC") { 15 }
+	})
+}
diff --git a/src/mainboard/google/ninja/acpi/superio.asl b/src/mainboard/google/ninja/acpi/superio.asl
new file mode 100644
index 0000000000..15b8062c6c
--- /dev/null
+++ b/src/mainboard/google/ninja/acpi/superio.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/ninja/ec.h>
+#include <mainboard/google/ninja/onboard.h>
+
+#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+// Override default IRQ settings
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ}
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/ninja/acpi/video.asl b/src/mainboard/google/ninja/acpi/video.asl
new file mode 100644
index 0000000000..1405b04031
--- /dev/null
+++ b/src/mainboard/google/ninja/acpi/video.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/ninja/acpi_tables.c b/src/mainboard/google/ninja/acpi_tables.c
new file mode 100644
index 0000000000..caff8a9656
--- /dev/null
+++ b/src/mainboard/google/ninja/acpi_tables.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+
+	/* Enable USB ports in S3 */
+	gnvs->s3u0 = 1;
+	gnvs->s3u1 = 1;
+
+	/* Disable USB ports in S5 */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* TPM Present */
+	gnvs->tpmp = 1;
+
+	/* Enable DPTF */
+	gnvs->dpte = 1;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	current = acpi_madt_irq_overrides(current);
+
+	return current;
+}
\ No newline at end of file
diff --git a/src/mainboard/google/ninja/board_info.txt b/src/mainboard/google/ninja/board_info.txt
new file mode 100644
index 0000000000..57ef3bc4cc
--- /dev/null
+++ b/src/mainboard/google/ninja/board_info.txt
@@ -0,0 +1,3 @@
+Category: half
+ROM protocol: SPI
+Flashrom support: y
diff --git a/src/mainboard/google/ninja/chromeos.c b/src/mainboard/google/ninja/chromeos.c
new file mode 100644
index 0000000000..baafb6f798
--- /dev/null
+++ b/src/mainboard/google/ninja/chromeos.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+#endif
+
+/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */
+#define WP_STATUS_PAD	36
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+int get_lid_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+	u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+
+	return !!(ec_switches & EC_SWITCH_LID_OPEN);
+#else
+	/* Default to force open. */
+	return 1;
+#endif
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+    struct lb_gpio chromeos_gpios[] = {
+		{ssus_get_gpio(WP_STATUS_PAD), ACTIVE_HIGH, 0, "write protect"},
+		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+		{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+	u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+	u32 ec_events;
+
+	/* If a switch is set, we don't need to look at events. */
+	if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
+		return 1;
+
+	/* Else check if the EC has posted the keyboard recovery event. */
+	ec_events = google_chromeec_get_events_b();
+
+	return !!(ec_events &
+		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+#else
+	return 0;
+#endif
+}
+
+int get_write_protect_state(void)
+{
+	/*
+	 * The vboot loader queries this function in romstage. The GPIOs have
+	 * not been set up yet as that configuration is done in ramstage. The
+	 * hardware defaults to an input but there is a 20K pulldown. Externally
+	 * there is a 10K pullup. Disable the internal pull in romstage so that
+	 * there isn't any ambiguity in the reading.
+	 */
+#if defined(__PRE_RAM__)
+	ssus_disable_internal_pull(WP_STATUS_PAD);
+#endif
+
+	/* WP is enabled when the pin is reading high. */
+	return ssus_get_gpio(WP_STATUS_PAD);
+}
\ No newline at end of file
diff --git a/src/mainboard/google/ninja/chromeos.fmd b/src/mainboard/google/ninja/chromeos.fmd
new file mode 100644
index 0000000000..113fba6e6f
--- /dev/null
+++ b/src/mainboard/google/ninja/chromeos.fmd
@@ -0,0 +1,38 @@
+FLASH@0xff800000 0x800000 {
+	SI_ALL@0x0 0x200000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x1ff000
+	}
+	SI_BIOS@0x200000 0x600000 {
+		RW_SECTION_A@0x0 0xf0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0xdffc0
+			RW_FWID_A@0xeffc0 0x40
+		}
+		RW_SECTION_B@0xf0000 0xf0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0xdffc0
+			RW_FWID_B@0xeffc0 0x40
+		}
+		RW_MRC_CACHE@0x1e0000 0x10000
+		RW_ELOG@0x1f0000 0x4000
+		RW_SHARED@0x1f4000 0x4000 {
+			SHARED_DATA@0x0 0x2000
+			VBLOCK_DEV@0x2000 0x2000
+		}
+		RW_VPD@0x1f8000 0x2000
+		RW_UNUSED@0x1fa000 0x6000
+		RW_LEGACY(CBFS)@0x200000 0x200000
+		WP_RO@0x400000 0x200000 {
+			RO_VPD@0x0 0x4000
+			RO_UNUSED@0x4000 0xc000
+			RO_SECTION@0x10000 0x1f0000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x100000
+			}
+		}
+	}
+}
diff --git a/src/mainboard/google/ninja/cmos.layout b/src/mainboard/google/ninja/cmos.layout
new file mode 100644
index 0000000000..f862cd68b7
--- /dev/null
+++ b/src/mainboard/google/ninja/cmos.layout
@@ -0,0 +1,135 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/ninja/devicetree.cb b/src/mainboard/google/ninja/devicetree.cb
new file mode 100644
index 0000000000..6d5613043e
--- /dev/null
+++ b/src/mainboard/google/ninja/devicetree.cb
@@ -0,0 +1,102 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Ninja board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+	register "usb2_comp_bg" = "0x4700"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 off end # PCIE_PORT2
+		device pci 1c.2 on  end # PCIE_PORT3
+		device pci 1c.3 on  end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/ninja/dsdt.asl b/src/mainboard/google/ninja/dsdt.asl
new file mode 100644
index 0000000000..6475e1c5cf
--- /dev/null
+++ b/src/mainboard/google/ninja/dsdt.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include <soc/intel/baytrail/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/baytrail/acpi/globalnvs.asl>
+
+	#include <soc/intel/baytrail/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			//#include <soc/intel/baytrail/acpi/northcluster.asl>
+			#include <soc/intel/baytrail/acpi/southcluster.asl>
+		}
+
+		/* Dynamic Platform Thermal Framework */
+		#include "acpi/dptf.asl"
+	}
+
+	#include "acpi/chromeos.asl"
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <soc/intel/baytrail/acpi/sleepstates.asl>
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/ninja/ec.c b/src/mainboard/google/ninja/ec.c
new file mode 100644
index 0000000000..994b211a03
--- /dev/null
+++ b/src/mainboard/google/ninja/ec.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+	printk(BIOS_DEBUG, "mainboard_ec_init\n");
+	post_code(0xf0);
+
+	/* Restore SCI event mask on resume. */
+	if (acpi_slp_type == 3) {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S3_WAKE_EVENTS);
+
+		/* Disable SMI and wake events */
+		google_chromeec_set_smi_mask(0);
+
+		/* Clear pending events */
+		while (google_chromeec_get_event() != 0);
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+	} else {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S5_WAKE_EVENTS);
+		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+	}
+
+	/* Clear wake events, these are enabled on entry to sleep */
+	google_chromeec_set_wake_mask(0);
+
+	post_code(0xf1);
+}
diff --git a/src/mainboard/google/ninja/ec.h b/src/mainboard/google/ninja/ec.h
new file mode 100644
index 0000000000..159351bed2
--- /dev/null
+++ b/src/mainboard/google/ninja/ec.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
+#define EC_SCI_GPI   24
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI   23
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/ninja/fadt.c b/src/mainboard/google/ninja/fadt.c
new file mode 100644
index 0000000000..2434d1afc1
--- /dev/null
+++ b/src/mainboard/google/ninja/fadt.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	acpi_fill_in_fadt(fadt);
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/ninja/gpio.c b/src/mainboard/google/ninja/gpio.c
new file mode 100644
index 0000000000..81f01baf79
--- /dev/null
+++ b/src/mainboard/google/ninja/gpio.c
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include "irqroute.h"
+
+/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_FUNC2,	/* S0_NC07 - DDI1_DDCDATA */
+	GPIO_FUNC2,	/* S0_NC08 - DDI1_DDCCLK */
+	GPIO_NC,	/* S0_NC09 - NC */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_NC,	/* S0_SC001 - NC */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE0# */
+	GPIO_NC,	/* S0-SC004 - NC# */
+	GPIO_FUNC1,	/* S0-SC005 - PCIE_CLKREQ_WLAN# */
+	GPIO_FUNC1,	/* S0-SC006 - PCIE_CLKREQ_LAN# */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_FUNC1,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_FUNC1,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_NC,	/* S0-SC055 - NC */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - NC */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_NC,	/* S0-SC076 - NC */
+	GPIO_NC,	/* S0-SC077 - NC */
+	GPIO_NC,	/* S0-SC078 - NC */
+	GPIO_NC,	/* S0-SC079 - NC */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_NC,	/* S0-SC086 - NC */
+	GPIO_NC,	/* S0-SC087 - NC */
+	GPIO_NC,	/* S0-SC088 - NC */
+	GPIO_NC,	/* S0-SC089 - NC */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_NC,	/* S501 - NC */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_INPUT,	/* S508 - SOC_RECOVER- */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/ninja/irqroute.c b/src/mainboard/google/ninja/irqroute.c
new file mode 100644
index 0000000000..db8c512a43
--- /dev/null
+++ b/src/mainboard/google/ninja/irqroute.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/google/ninja/irqroute.h b/src/mainboard/google/ninja/irqroute.h
new file mode 100644
index 0000000000..988aaf4ba3
--- /dev/null
+++ b/src/mainboard/google/ninja/irqroute.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,   C, D, E, F), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(MMC_DEV,  D, E, F, G), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,  A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+	PIRQ_PIC(A, DISABLE), \
+	PIRQ_PIC(B, DISABLE), \
+	PIRQ_PIC(C, DISABLE), \
+	PIRQ_PIC(D, DISABLE), \
+	PIRQ_PIC(E, DISABLE), \
+	PIRQ_PIC(F, DISABLE), \
+	PIRQ_PIC(G, DISABLE), \
+	PIRQ_PIC(H, DISABLE)
+
+/* CORE bank DIRQs - up to 16 supported */
+#define I8042_IRQ_OFFSET	2
+/* Corresponding SCORE GPIO pins */
+#define I8042_IRQ_GPIO		101
+
+/* SUS bank DIRQs - up to 16 supported */
+#define CODEC_IRQ_OFFSET	0
+/* Corresponding SUS GPIO pins */
+#define CODEC_IRQ_GPIO		9
diff --git a/src/mainboard/google/ninja/lan.c b/src/mainboard/google/ninja/lan.c
new file mode 100644
index 0000000000..dad8692253
--- /dev/null
+++ b/src/mainboard/google/ninja/lan.c
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <string.h>
+#include <types.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <fmap.h>
+#include "onboard.h"
+
+static unsigned int search(char *p, u8 *a, unsigned int lengthp,
+			   unsigned int lengtha)
+{
+	int i, j;
+
+	/* Searching */
+	for (j = 0; j <= lengtha - lengthp; j++) {
+		for (i = 0; i < lengthp && p[i] == a[i + j]; i++)
+			;
+		if (i >= lengthp)
+			return j;
+	}
+	return lengtha;
+}
+
+static unsigned char get_hex_digit(u8 *offset)
+{
+	unsigned char retval = 0;
+
+	retval = *offset - '0';
+	if (retval > 0x09) {
+		retval = *offset - 'A' + 0x0A;
+		if (retval > 0x0F)
+			retval = *offset - 'a' + 0x0a;
+	}
+	if (retval > 0x0F) {
+		printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n",
+			*offset, *offset);
+		retval = 0;
+	}
+
+	return retval;
+}
+
+static int get_mac_address(u32 *high_dword, u32 *low_dword,
+			   u8 *search_address, u32 search_length)
+{
+	char key[] = "ethernet_mac";
+	unsigned int offset;
+	int i;
+
+	offset = search(key, search_address, sizeof(key) - 1, search_length);
+	if (offset == search_length) {
+		printk(BIOS_DEBUG,
+		       "Error: Could not locate '%s' in VPD\n", key);
+		return 0;
+	}
+	printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
+
+	offset += sizeof(key);	/* move to next character */
+	*high_dword = 0;
+
+	/* Fetch the MAC address and put the octets in the correct order to
+	 * be programmed.
+	 *
+	 * From RTL8105E_Series_EEPROM-Less_App_Note_1.1
+	 * If the MAC address is 001122334455h:
+	 * Write 33221100h to I/O register offset 0x00 via double word access
+	 * Write 00005544h to I/O register offset 0x04 via double word access
+	 */
+
+	for (i = 0; i < 4; i++) {
+		*high_dword |= (get_hex_digit(search_address + offset)
+				<< (4 + (i * 8)));
+		*high_dword |= (get_hex_digit(search_address + offset + 1)
+				<< (i * 8));
+		offset += 3;
+	}
+
+	*low_dword = 0;
+	for (i = 0; i < 2; i++) {
+		*low_dword |= (get_hex_digit(search_address + offset)
+			       << (4 + (i * 8)));
+		*low_dword |= (get_hex_digit(search_address + offset + 1)
+			       << (i * 8));
+		offset += 3;
+	}
+
+	return *high_dword | *low_dword;
+}
+
+static void program_mac_address(u16 io_base)
+{
+	void *search_address = NULL;
+	size_t search_length = -1;
+
+	/* Default MAC Address of A0:00:BA:D0:0B:AD */
+	u32 high_dword = 0xD0BA00A0;	/* high dword of mac address */
+	u32 low_dword = 0x0000AD0B;	/* low word of mac address as a dword */
+
+	if (IS_ENABLED(CONFIG_CHROMEOS)) {
+		struct region_device rdev;
+
+		if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
+			search_address = rdev_mmap_full(&rdev);
+
+			if (search_address != NULL)
+				search_length = region_device_sz(&rdev);
+		}
+	} else {
+		search_address = cbfs_boot_map_with_leak("vpd.bin",
+							CBFS_TYPE_RAW,
+							&search_length);
+	}
+
+	if (search_address == NULL)
+		printk(BIOS_ERR, "LAN: VPD not found.\n");
+	else
+		get_mac_address(&high_dword, &low_dword, search_address,
+				search_length);
+
+	if (io_base) {
+		printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
+		printk(BIOS_DEBUG, "Programming MAC Address\n");
+
+		/* Disable register protection */
+		outb(0xc0, io_base + 0x50);
+		outl(high_dword, io_base);
+		outl(low_dword, io_base + 0x04);
+		outb(0x60, io_base + 54);
+		/* Enable register protection again */
+		outb(0x00, io_base + 0x50);
+	}
+}
+
+void lan_init(void)
+{
+	u16 io_base = 0;
+	struct device *ethernet_dev = NULL;
+
+	/* Get NIC's IO base address */
+	ethernet_dev = dev_find_device(NINJA_NIC_VENDOR_ID,
+				       NINJA_NIC_DEVICE_ID, 0);
+	if (ethernet_dev != NULL) {
+		io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
+
+		/*
+		 * Battery life time - LAN PCIe should enter ASPM L1 to save
+		 * power when LAN connection is idle.
+		 * enable CLKREQ: LAN pci config space 0x81h=01
+		 */
+		pci_write_config8(ethernet_dev, 0x81, 0x01);
+	}
+
+	if (io_base) {
+		/* Program MAC address based on VPD data */
+		program_mac_address(io_base);
+
+		/*
+		 * Program NIC LEDS
+		 *
+		 * RTL8105E Series EEPROM-Less Application Note,
+		 * Section 5.6 LED Mode Configuration
+		 *
+		 * Step1: Write C0h to I/O register 0x50 via byte access to
+		 *        disable 'register protection'
+		 * Step2: Write xx001111b to I/O register 0x52 via byte access
+		 *        (bit7 is LEDS1 and bit6 is LEDS0)
+		 * Step3: Write 0x00 to I/O register 0x50 via byte access to
+		 *        enable 'register protection'
+		 */
+		outb(0xc0, io_base + 0x50);	/* Disable protection */
+		outb((NINJA_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
+		outb(0x00, io_base + 0x50);	/* Enable register protection */
+	}
+}
diff --git a/src/mainboard/google/ninja/mainboard.c b/src/mainboard/google/ninja/mainboard.c
new file mode 100644
index 0000000000..a5d171eac7
--- /dev/null
+++ b/src/mainboard/google/ninja/mainboard.c
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <smbios.h>
+#include "ec.h"
+#include "onboard.h"
+#include <soc/gpio.h>
+#include <bootstate.h>
+
+void mainboard_suspend_resume(void)
+{
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+	int res = 1;
+
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+	       __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+	switch (X86_AX) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		X86_AX = 0x005f;
+		X86_CX = 0x0001;
+		res = 1;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV
+		 *  bit 2 = EFP (HDMI)
+		 *  bit 3 = LFP (eDP)*
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		X86_AX = 0x005f;
+		X86_CX = 0x0000;
+		res = 1;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		X86_AX = 0x005f;
+		X86_CX = 0x0003;
+		res = 1;
+		break;
+	case 0x5f70:
+		switch ((X86_CX >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			X86_AX = 0x005f;
+			X86_CX = 0x0000;
+			res = 1;
+			break;
+		case 1:
+			/* Set Mux */
+			X86_AX = 0x005f;
+			X86_CX = 0x0000;
+			res = 1;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			X86_AX = 0x005f;
+			X86_CX = 0x0000;
+			res = 1;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG,
+			       "Unknown INT15 5f70 function: 0x%02x\n",
+				((X86_CX >> 8) & 0xff));
+			break;
+		}
+		break;
+
+	default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+		break;
+	}
+	return res;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+	mainboard_ec_init();
+	lan_init();
+}
+
+static int mainboard_smbios_data(device_t dev, int *handle,
+				 unsigned long *current)
+{
+	return 0;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+	dev->ops->get_smbios_data = mainboard_smbios_data;
+#if CONFIG_VGA_ROM_RUN
+	/* Install custom int15 handler for VGA OPROM */
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
+
+static void edp_vdden_cb(void *unused)
+{
+	ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL);
diff --git a/src/mainboard/google/ninja/mainboard_smi.c b/src/mainboard/google/ninja/mainboard_smi.c
new file mode 100644
index 0000000000..bb0f4fb787
--- /dev/null
+++ b/src/mainboard/google/ninja/mainboard_smi.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+#include <soc/nvs.h>
+#include <soc/pmc.h>
+
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		smm_get_gnvs()->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+static uint8_t mainboard_smi_ec(void)
+{
+	uint8_t cmd = google_chromeec_get_event();
+	uint16_t pmbase = get_pmbase();
+	uint32_t pm1_cnt;
+
+#if CONFIG_ELOG_GSMI
+	/* Log this event */
+	if (cmd)
+		elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+#endif
+
+	switch (cmd) {
+	case EC_HOST_EVENT_LID_CLOSED:
+		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+		/* Go to S5 */
+		pm1_cnt = inl(pmbase + PM1_CNT);
+		pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+		outl(pm1_cnt, pmbase + PM1_CNT);
+		break;
+	}
+
+	return cmd;
+}
+
+/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits. */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
+{
+	if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
+		/* Process all pending events */
+		while (mainboard_smi_ec() != 0);
+	}
+}
+
+void mainboard_smi_sleep(uint8_t slp_typ)
+{
+	/* Disable USB charging if required */
+	switch (slp_typ) {
+	case 3:
+		if (smm_get_gnvs()->s3u0 == 0)
+			google_chromeec_set_usb_charge_mode(
+				0, USB_CHARGE_MODE_DISABLED);
+		if (smm_get_gnvs()->s3u1 == 0)
+			google_chromeec_set_usb_charge_mode(
+				1, USB_CHARGE_MODE_DISABLED);
+
+		/* Enable wake events */
+		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+		/* Enable wake pin in GPE block. */
+		enable_gpe(WAKE_GPIO_EN);
+		break;
+	case 5:
+		if (smm_get_gnvs()->s5u0 == 0)
+			google_chromeec_set_usb_charge_mode(
+				0, USB_CHARGE_MODE_DISABLED);
+		if (smm_get_gnvs()->s5u1 == 0)
+			google_chromeec_set_usb_charge_mode(
+				1, USB_CHARGE_MODE_DISABLED);
+
+		/* Enable wake events */
+		google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
+		break;
+	}
+
+	/* Disable SCI and SMI events */
+	google_chromeec_set_smi_mask(0);
+	google_chromeec_set_sci_mask(0);
+
+	/* Clear pending events that may trigger immediate wake */
+	while (google_chromeec_get_event() != 0);
+}
+
+int mainboard_smi_apmc(uint8_t apmc)
+{
+	switch (apmc) {
+	case APM_CNT_ACPI_ENABLE:
+		google_chromeec_set_smi_mask(0);
+		/* Clear all pending events */
+		while (google_chromeec_get_event() != 0);
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+		break;
+	case APM_CNT_ACPI_DISABLE:
+		google_chromeec_set_sci_mask(0);
+		/* Clear all pending events */
+		while (google_chromeec_get_event() != 0);
+		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
+		break;
+	}
+	return 0;
+}
diff --git a/src/mainboard/google/ninja/onboard.h b/src/mainboard/google/ninja/onboard.h
new file mode 100644
index 0000000000..5a01bb4106
--- /dev/null
+++ b/src/mainboard/google/ninja/onboard.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include "irqroute.h"
+
+#ifndef __ACPI__
+void lan_init(void);
+#endif
+
+/* defines for programming the MAC address */
+#define NINJA_NIC_VENDOR_ID			0x10EC
+#define NINJA_NIC_DEVICE_ID			0x8168
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define NINJA_NIC_LED_MODE				0x00
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/ninja/romstage.c b/src/mainboard/google/ninja/romstage.c
new file mode 100644
index 0000000000..271d144bee
--- /dev/null
+++ b/src/mainboard/google/ninja/romstage.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ */
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
+{
+	int ram_id = 0;
+
+	/* The ram_id[2:0] pullups on ninja are too large for the default 20K
+	 * pulldown on the pad. Therefore, disable the internal pull resistor to
+	 * read high values correctly. */
+	ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
+	ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
+	ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
+
+	ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
+	ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
+	ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
+
+	printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+
+	if (ram_id >= total_spds)
+		return NULL;
+
+	/* Single channel configs */
+	if (dual_channel_config & (1 << ram_id))
+		*dual = 1;
+
+	return &spd_file_content[SPD_SIZE * ram_id];
+}
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+	void *spd_content;
+	int dual_channel = 0;
+	void *spd_file;
+	size_t spd_fsize;
+
+	struct mrc_params mp = {
+		.mainboard = {
+			.dram_type = DRAM_DDR3L,
+			.dram_info_location = DRAM_INFO_SPD_MEM,
+			.weaker_odt_settings = 1,
+		},
+	};
+
+	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+						&spd_fsize);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	/* Both channels are always present. */
+	spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
+	                              &dual_channel);
+	mp.mainboard.dram_data[0] = spd_content;
+	if (dual_channel)
+		mp.mainboard.dram_data[1] = spd_content;
+
+	rp->mrc_params = &mp;
+	romstage_common(rp);
+}
diff --git a/src/mainboard/google/ninja/spd/Makefile.inc b/src/mainboard/google/ninja/spd/Makefile.inc
new file mode 100644
index 0000000000..9b4e8c13ea
--- /dev/null
+++ b/src/mainboard/google/ninja/spd/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/ninja/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/ninja/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
new file mode 100644
index 0000000000..4bd8e0eca6
--- /dev/null
+++ b/src/mainboard/google/ninja/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 03 11 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+00 05 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 22 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 41 5f
+48 4d 54 33 31 32 53 36
+44 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000000..ff4fd29862
--- /dev/null
+++ b/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex b/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex
new file mode 100644
index 0000000000..8ced79063f
--- /dev/null
+++ b/src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6CFR6A-PBA
+92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/ninja/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/ninja/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
new file mode 100644
index 0000000000..f99c92a2a7
--- /dev/null
+++ b/src/mainboard/google/ninja/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 03 11 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+50 00 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 6a 15
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/ninja/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/ninja/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
new file mode 100644
index 0000000000..f3bcb56245
--- /dev/null
+++ b/src/mainboard/google/ninja/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+20 08 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 19 d2
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/ninja/w25q64.c b/src/mainboard/google/ninja/w25q64.c
new file mode 100644
index 0000000000..a9ed8ac98b
--- /dev/null
+++ b/src/mainboard/google/ninja/w25q64.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/spi.h>
+
+/*
+ * SPI lockdown configuration W25Q64FW.
+ */
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
+		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
+		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct spi_config spi_config = {
+	.preop = SPI_OPPREFIX,
+	.optype = SPI_OPTYPE,
+	.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+	.lvscc =  SPI_VSCC,
+	.uvscc =  SPI_VSCC,
+};
+
+int mainboard_get_spi_config(struct spi_config *cfg)
+{
+	memcpy(cfg, &spi_config, sizeof(*cfg));
+
+	return 0;
+}