Combine Baytrail ChromeOS devices using variant scheme

Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.

Variants contain board specific data:
 - DPTF ACPI components
 - I2C ACPI devices
 - RAM config / SPD data
 - devicetree config
 - GPIOs
 - board-specific HW components (e.g., LAN)

Additionally, some minor cleanup/changes were made:
 - remove unused ACPI trackpad/touchscreen devices
 - correct I2C addresses in SMBIOS entries
 - clean up comment formatting
 - remove ACPI device for unused light sensor
 - switch I2C ACPI devices from edge to level triggered interrupts,
   for better compatibility/functionality (and to be consistent
   with other recently-upstreamed ChromeOS devices)

The existing enguarde and ninja boards are removed.

Variant setup modeled after google/auron

Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 0 insertions, 54 deletions

diff --git a/src/mainboard/google/ninja/irqroute.h b/src/mainboard/google/ninja/irqroute.h
deleted file mode 100644
index 988aaf4ba3..0000000000
--- a/src/mainboard/google/ninja/irqroute.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/irq.h>
-#include <soc/pci_devs.h>
-#include <soc/pmc.h>
-
-#define PCI_DEV_PIRQ_ROUTES \
-	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(SD_DEV,   C, D, E, F), \
-	PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(LPE_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(MMC_DEV,  D, E, F, G), \
-	PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(TXE_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(HDA_DEV,  A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
-	PCI_DEV_PIRQ_ROUTE(PCU_DEV,  A, B, C, D)
-
-#define PIRQ_PIC_ROUTES \
-	PIRQ_PIC(A, DISABLE), \
-	PIRQ_PIC(B, DISABLE), \
-	PIRQ_PIC(C, DISABLE), \
-	PIRQ_PIC(D, DISABLE), \
-	PIRQ_PIC(E, DISABLE), \
-	PIRQ_PIC(F, DISABLE), \
-	PIRQ_PIC(G, DISABLE), \
-	PIRQ_PIC(H, DISABLE)
-
-/* CORE bank DIRQs - up to 16 supported */
-#define I8042_IRQ_OFFSET	2
-/* Corresponding SCORE GPIO pins */
-#define I8042_IRQ_GPIO		101
-
-/* SUS bank DIRQs - up to 16 supported */
-#define CODEC_IRQ_OFFSET	0
-/* Corresponding SUS GPIO pins */
-#define CODEC_IRQ_GPIO		9