diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2015-10-20 19:36:09 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-05-31 21:15:27 +0200 |
commit | a87fcabd2efe49c8035b76146401e190a0ea6593 (patch) | |
tree | 9cbb2fcef19484ebf5c96aa6211468c25d09a1d2 /src/mainboard/google/ninja/devicetree.cb | |
parent | 4acb0e774220c0705a71689b6620c976297d417c (diff) |
google/ninja: Upstream AOpen Chromebox Commerical
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-ninja-5216.383.B
commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA]
TEST=built and booted Linux on ninja with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/14950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/ninja/devicetree.cb')
-rw-r--r-- | src/mainboard/google/ninja/devicetree.cb | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/src/mainboard/google/ninja/devicetree.cb b/src/mainboard/google/ninja/devicetree.cb new file mode 100644 index 0000000000..6d5613043e --- /dev/null +++ b/src/mainboard/google/ninja/devicetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for Ninja board + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # Enable devices in ACPI mode + register "lpe_acpi_mode" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # Enable PIPEA as DP_C + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "6" # 600ms + register "gpu_pipea_power_on_delay" = "5000" # 500ms + register "gpu_pipea_light_on_delay" = "70" # 7ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 off end # PCIE_PORT2 + device pci 1c.2 on end # PCIE_PORT3 + device pci 1c.3 on end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge + device pci 1f.3 off end # SMBus + end +end |