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authorNitheesh Sekar <nsekar@codeaurora.org>2018-09-14 11:48:46 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-03-18 18:17:12 +0000
commit918fc00fb40fb847acc4f4c8c9e9657b5e283e68 (patch)
tree676146a46b51fe24b07d3e1c56ee4fc6cced4d5e /src/mainboard/google/mistral/devicetree.cb
parent20e75878a8ff47d18d87cd8d213d044cffcaeee7 (diff)
mainboard/google/mistral: Add support for Mistral
Adding a new board variant 'Mistral' based on qcs405 soc. TEST=build Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/mistral/devicetree.cb')
-rw-r--r--src/mainboard/google/mistral/devicetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/mistral/devicetree.cb b/src/mainboard/google/mistral/devicetree.cb
new file mode 100644
index 0000000000..977f4c68d9
--- /dev/null
+++ b/src/mainboard/google/mistral/devicetree.cb
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 and
+## only version 2 as published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/qualcomm/qcs405
+ device cpu_cluster 0 on end
+end