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authorKarthikeyan Ramasubramanian <kramasub@google.com>2021-05-19 12:06:58 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-05-21 11:23:24 +0000
commita1a8c2c621a4ae1e093c63e6b1c34b049da5f0b8 (patch)
tree83dc9c2d9f1895f52e2afcd9622bdb757b23524f /src/mainboard/google/mancomb
parentdd4861ae04a7825f04470471fe56cc4fc46028dc (diff)
mb/google/mancomb: Enable S0ix
BUG=b:188446049 TEST=Build and boot to OS in mancomb. Ensure that the system can suspend and resume successfully. Ensure that the sleep state GPIOs are reflecting the state as expected. Change-Id: I43e86a07075fe66f89c2c5665adc209e985e4f04 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/mancomb')
-rw-r--r--src/mainboard/google/mancomb/variants/baseboard/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
index c3a830605b..c37b45517c 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
@@ -47,6 +47,9 @@ chip soc/amd/cezanne
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+ # Enable S0i3 support
+ register "s0ix_enable" = "1"
+
device domain 0 on
device ref gpp_bridge_0 on end # WLAN
device ref gpp_bridge_1 on end # SD