diff options
| author | Keith Hui <buurin@gmail.com> | 2024-02-05 19:18:43 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-08 00:19:23 +0000 |
| commit | a911b758482025d46e132eeb2ed0279b65692075 (patch) | |
| tree | fb8475ef03a0365132fefb82bc248468ef0a4784 /src/mainboard/google/link | |
| parent | ee126348726b24fbf6e5435bb2cf15417959a8f7 (diff) | |
mb/*: Remove old USB configurations from SNB/bd82x6x boards
Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/link')
| -rw-r--r-- | src/mainboard/google/link/devicetree.cb | 16 | ||||
| -rw-r--r-- | src/mainboard/google/link/early_init.c | 18 |
2 files changed, 0 insertions, 34 deletions
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index f14728f643..028db5e528 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index e40531dac1..2d20ac03a9 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -63,24 +63,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, -1 }, /* P3: SDCARD (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 1, 0, -1 }, /* P5: WWAN (no OC) */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: Camera (no OC) */ - { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ - { 0, 0, -1 }, /* P10: Empty */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { /* LINK has 2 channels of memory down */ |