sandy/ivy/nehalem: Remerge interrupt handling

On those chipsets the pins are just a legacy concept. Real interrupts are
messages on corresponding busses or some internal logic of chipset.
Hence interrupt routing isn't anymore board-specific (dependent on layout) but
depends only on configuration.
Rather than attempting to sync real config, ACPI and legacy descriptors, just
use the same interrupt routing per chipset covering all possible devices.

The only part which remains board-specific are LPC and PCI interrupts.

Interrupt balancing may suffer from such merge but:
a) Doesn't seem to be the case of this map on current systems
b) Almost all OS use MSI nowadays bypassing this stuff completely
c) If we want a good balancing we need to take into account that e.g.
   wlan card may be placed in a different slot and so would require complicated
   balancing on runtime. It's difficult to maintain with almost no benefit.

Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7130
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

4 files changed, 1 insertions, 133 deletions

diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index a4267bb253..0000000000
--- a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 16 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 19 },
-			Package() { 0x001cffff, 1, 0, 20 },
-			Package() { 0x001cffff, 2, 0, 17 },
-			Package() { 0x001cffff, 3, 0, 18 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, 0, 21 },
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 17 },
-			Package() { 0x001fffff, 1, 0, 23 },
-			Package() { 0x001fffff, 2, 0, 16 },
-			Package() { 0x001fffff, 3, 0, 18 },
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index 14baad2d45..d1d4fcba18 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -83,24 +83,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->lids = 1;
 }
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
 unsigned long acpi_fill_slit(unsigned long current)
 {
 	// Not implemented
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 15aa432e64..5333dfc2c3 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -42,15 +42,6 @@ chip northbridge/intel/sandybridge
 		device pci 02.0 on end # vga controller
 
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
 			# GPI routing
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 8236e2062d..f90d7e7728 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -78,44 +78,7 @@ static void rcba_config(void)
 {
 	u32 reg32;
 
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P3IP  WLAN   INTA -> PIRQB
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D26IP_E2P   EHCI2  INTA -> PIRQF
-	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
-	 * D31IP_TTIP  THRT   INTC -> PIRQA
-	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-	 *
-	 * TRACKPAD                -> PIRQE (Edge Triggered)
-	 * TOUCHSCREEN             -> PIRQG (Edge Triggered)
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
-	RCBA32(D30IP) = (NOINT << D30IP_PIP);
-	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P3IP);
-	RCBA32(D27IP) = (INTA << D27IP_ZIP);
-	RCBA32(D26IP) = (INTA << D26IP_E2P);
-	RCBA32(D25IP) = (NOINT << D25IP_LIP);
-	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
-	/* Device interrupt route registers */
-	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
-	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
-	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
-	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
-	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
-	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
-	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
-	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
-	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	southbridge_configure_default_intmap();
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);