google/link: Use common i915_reg.h.

Checked by comparing binaries and seeing no differences other than
build info.

Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6819
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

1 files changed, 7 insertions, 7 deletions

diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c
index abceb05f1b..4bf0e6fd86 100644
--- a/src/mainboard/google/link/i915io.c
+++ b/src/mainboard/google/link/i915io.c
@@ -107,12 +107,12 @@ struct iodef iodefs[] = {
 	{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0},
 	{W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0},
 	{R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200},
-	{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
+	{W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0},
 	{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
 	{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
 	{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
 	{W, 1, "", 0x9404, 0x00002000, 0},
-	{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
+	{W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0},
 	{W, 1, "", IVB_CHICKEN3, 0x00000024, 0},
 	{W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0},
 	{W, 1, "", 0xb01c, 0x3c4fff8c, 0},
@@ -141,7 +141,7 @@ struct iodef iodefs[] = {
 	{R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0},
 	{W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0},
 	{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
-	{W, 1, "", _TRANSB_CHICKEN2, TRANS_AUTOTRAIN_GEN_STALL_DIS | 0x80000000, 0},
+	{W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0},
 	{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0},
 	{M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0},
 	{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0},
@@ -199,13 +199,13 @@ struct iodef iodefs[] = {
 	{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
 	{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
 	{R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
-	{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
+	{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
 	{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
 	{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
 	{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
 	{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
 	{W, 1, "", _DSPAADDR, 0x00000000, 0},
-	{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
+	{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
 	{R, 1, "", 0x145d10, 0x2010040c, 0},
 	{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
 	{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
@@ -274,8 +274,8 @@ struct iodef iodefs[] = {
 	{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
 	{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
 	{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
-	{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
-	{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0xd8004000, 0},
+	{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
+	{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0xd8004000, 0},
 	{R, 1, "", _DSPAADDR, 0x00000000, 0},
 	{W, 1, "", _DSPAADDR, 0x00000000, 0},
 	{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},