diff options
| author | Keith Hui <buurin@gmail.com> | 2024-02-05 16:44:38 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-08 00:08:33 +0000 |
| commit | 51a57eb5ea782c3287719c8c7646ea726b14c78d (patch) | |
| tree | 7ff3a6b1424750e66d4349f41eeb7fcc7b10ab77 /src/mainboard/google/link/devicetree.cb | |
| parent | 1acb3e118bf0bdba8f13f62304425f8c21dad2c8 (diff) | |
mb/*: Add consolidated USB port config for SNB+MRC boards
For each sandybridge boards with option to use MRC or native platform
init code, add a copy of the board's USB port config, consolidated between
both code paths, into the southbridge devicetree, using special values
allocated for this consolidation.
These get hooked up in a separate patch.
Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/link/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/link/devicetree.cb | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 88983dcfc6..f14728f643 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -65,6 +65,23 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, -1 }, /* P3: SDCARD (no OC) */ + { 0, 0, -1 }, /* P4: Empty */ + { 1, 0, -1 }, /* P5: WWAN (no OC) */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, -1 }, /* P8: Camera (no OC) */ + { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ + { 0, 0, -1 }, /* P10: Empty */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R |