diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-06-06 17:13:42 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-06-09 17:07:26 +0200 |
| commit | 7f3156dad67ad35f02afedd85cdf4a19e3c0875e (patch) | |
| tree | 4584c4d6f24327279abf6de0864e0daffdf3fe48 /src/mainboard/google/lars | |
| parent | 205ed2d2b58f9b93c7c665002aef0c775e64cf63 (diff) | |
skylake: gpio: Add support for setting 1.8V tolerant
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
that are at 1.8V. This is currently done by passing in a value to FSP
but it is needed earlier than FSP if the I2C bus is used in verstage.
This does not remove the need for the FSP input parameter, that is
still required so FSP doesn't disable what has been set in coreboot.
The mainboards that are affected are updated in this commit.
This was tested by exercising I2C transactions to the 1.8V codec while
in verstage on the google/chell mainboard.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
Reviewed-on: https://review.coreboot.org/15103
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/lars')
| -rw-r--r-- | src/mainboard/google/lars/gpio.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index e1877957ac..40960a7299 100644 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -184,8 +184,8 @@ static const struct pad_config gpio_table[] = { /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* I2C3_SDA */ /* GPP_F6 */ /* I2C3_SCL */ /* GPP_F7 */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), |