diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-07-21 23:47:38 +0530 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-28 05:17:03 +0200 |
| commit | 50b9258a0bbe6cf99606c87a5b9b835ff0689a7d (patch) | |
| tree | ca83e704fdc3e5b73f0dd6e6655f9531fc110ebc /src/mainboard/google/lars | |
| parent | e4a8537ce20d801a5985ba6268ae83593063a4bf (diff) | |
skylake/mainboard: Define mainboard hook in bootblock
Move mainboard post console init functionality (google_chrome_ec_init &
early_gpio programming) from verstage to bootblock.
Add chromeos-ec support in bootblock
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu till POST code 0x34
Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15786
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/lars')
| -rw-r--r-- | src/mainboard/google/lars/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/mainboard/google/lars/bootblock_mainboard.c (renamed from src/mainboard/google/lars/car.c) | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/lars/Makefile.inc b/src/mainboard/google/lars/Makefile.inc index 4bf6e0ab41..cafa12ca60 100644 --- a/src/mainboard/google/lars/Makefile.inc +++ b/src/mainboard/google/lars/Makefile.inc @@ -16,10 +16,12 @@ subdirs-y += spd +bootblock-y += bootblock_mainboard.c + romstage-y += boardid.c -romstage-y += car.c romstage-y += pei_data.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -32,5 +34,3 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -verstage-y += car.c diff --git a/src/mainboard/google/lars/car.c b/src/mainboard/google/lars/bootblock_mainboard.c index 7791b92980..d514622442 100644 --- a/src/mainboard/google/lars/car.c +++ b/src/mainboard/google/lars/bootblock_mainboard.c @@ -13,20 +13,20 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <ec/google/chromeec/ec.h> -#include <fsp/car.h> #include <soc/gpio.h> #include "gpio.h" static void early_config_gpio(void) { /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't be. We have to prepare certain gpios here + * which it shouldn't do. We have to prepare certain gpios here * because of the brokenness in FSP. */ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } -void car_mainboard_post_console_init(void) +void bootblock_mainboard_init(void) { /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); |