diff options
author | david <david_wu@quantatw.com> | 2015-10-23 20:22:22 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-28 22:27:24 +0100 |
commit | ad038c1a14d595c88fb0b4bb6f420e4490b0a67a (patch) | |
tree | 6f9c0e0e43d7215d73749323def186bef015de00 /src/mainboard/google/lars/spd/spd.h | |
parent | 6ce7459d6712669b8b8b7579e10a639f4a32371f (diff) |
google/lars: Copy from intel/kunimitsu
Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12200
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/lars/spd/spd.h')
-rw-r--r-- | src/mainboard/google/lars/spd/spd.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h new file mode 100644 index 0000000000..eaa873b55a --- /dev/null +++ b/src/mainboard/google/lars/spd/spd.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 +#define SPD_MANU_OFF 148 + +#endif |