diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-07 19:03:06 -0500 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-07-21 00:49:52 +0000 |
commit | 357ea55f454a77dd5c2a9b14e5d7d5946b433146 (patch) | |
tree | d4440490f46869dddaeb620ecf975eef89869e54 /src/mainboard/google/lars/romstage.c | |
parent | 39f3c7e1840823c294d7cedf11aed62bdd765141 (diff) |
google/lars: Convert to a variant of glados
Convert lars to a variant of glados Skylake reference board:
- add lars-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add conditional generation of NHLT ACPI data for Maxim codec,
including override of OEM ID and OEM table ID
- remove existing lars board/directory
Test: build/boot google/lars, verify functionality unchanged
from pre-variant configuration
Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27413
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/lars/romstage.c')
-rw-r--r-- | src/mainboard/google/lars/romstage.c | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/src/mainboard/google/lars/romstage.c b/src/mainboard/google/lars/romstage.c deleted file mode 100644 index b3ef0d8d7a..0000000000 --- a/src/mainboard/google/lars/romstage.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <gpio.h> -#include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> -#include "gpio.h" -#include "spd/spd.h" - -void mainboard_romstage_entry(struct romstage_params *params) -{ - /* PCH_MEM_CFG[3:0] */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - /* Turn on keyboard backlight to indicate we are booting */ - if (params->power_state->prev_sleep_state != ACPI_S3) - google_chromeec_kbbacklight(25); - - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, - ARRAY_SIZE(spd_gpios)); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); - /* Initialize memory */ - romstage_common(params); -} - -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - } - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); - memory_params->MemorySpdDataLen = SPD_LEN; - memory_params->DqPinsInterleaved = FALSE; -} |