diff options
| author | david <david_wu@quantatw.com> | 2015-10-23 20:22:22 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-28 22:27:24 +0100 |
| commit | ad038c1a14d595c88fb0b4bb6f420e4490b0a67a (patch) | |
| tree | 6f9c0e0e43d7215d73749323def186bef015de00 /src/mainboard/google/lars/dsdt.asl | |
| parent | 6ce7459d6712669b8b8b7579e10a639f4a32371f (diff) | |
google/lars: Copy from intel/kunimitsu
Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12200
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/lars/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/lars/dsdt.asl | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl new file mode 100644 index 0000000000..ba1b2637c1 --- /dev/null +++ b/src/mainboard/google/lars/dsdt.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} |