diff options
| author | Mengqi Zhang <Mengqi.Zhang@mediatek.com> | 2019-04-24 11:11:52 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:38:41 +0000 |
| commit | 026be3d76f3934eb901485acd98e0d84f137068f (patch) | |
| tree | c269b874ad1fccd60889cc0fac94dd1f746608a7 /src/mainboard/google/kukui | |
| parent | 89b1753c2289edacca05ef46e840f212f2a3025d (diff) | |
mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/kukui')
| -rw-r--r-- | src/mainboard/google/kukui/bootblock.c | 7 | ||||
| -rw-r--r-- | src/mainboard/google/kukui/early_init.c | 2 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 9a7e71c292..ebd1e18d15 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -19,8 +19,11 @@ void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz); - mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz, + 0); + mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz, + 0); gpio_set_spi_driving(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 10); + } diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index 1193bb3fe9..7eee080412 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -34,6 +34,6 @@ void mainboard_early_init(void) gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0); - mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); } |